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[SystemZ] Add the MVC instruction

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This is the first use of D(L,B) addressing, which required a fair bit
of surgery.  For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-07-02 14:56:45 +00:00
parent 850ba41ed4
commit 9188443a2d
11 changed files with 328 additions and 130 deletions
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209
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
View File

@ -29,19 +29,25 @@ static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
}
namespace {
enum RegisterKind {
GR32Reg,
GR64Reg,
GR128Reg,
ADDR32Reg,
ADDR64Reg,
FP32Reg,
FP64Reg,
FP128Reg
};
enum MemoryKind {
BDMem,
BDXMem,
BDLMem
};
class SystemZOperand : public MCParsedAsmOperand {
public:
enum RegisterKind {
GR32Reg,
GR64Reg,
GR128Reg,
ADDR32Reg,
ADDR64Reg,
FP32Reg,
FP64Reg,
FP128Reg
};
private:
enum OperandKind {
KindInvalid,
@ -77,12 +83,15 @@ private:
// Base + Disp + Index, where Base and Index are LLVM registers or 0.
// RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
// Length is the operand length for D(L,B)-style operands, otherwise
// it is null.
struct MemOp {
unsigned Base : 8;
unsigned Index : 8;
unsigned RegKind : 8;
unsigned Unused : 8;
const MCExpr *Disp;
const MCExpr *Length;
};
union {
@ -139,12 +148,14 @@ public:
}
static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
const MCExpr *Disp, unsigned Index,
SMLoc StartLoc, SMLoc EndLoc) {
const MCExpr *Length, SMLoc StartLoc,
SMLoc EndLoc) {
SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
Op->Mem.RegKind = RegKind;
Op->Mem.Base = Base;
Op->Mem.Index = Index;
Op->Mem.Disp = Disp;
Op->Mem.Length = Length;
return Op;
}
@ -191,16 +202,20 @@ public:
virtual bool isMem() const LLVM_OVERRIDE {
return Kind == KindMem;
}
bool isMem(RegisterKind RegKind, bool HasIndex) const {
bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
return (Kind == KindMem &&
Mem.RegKind == RegKind &&
(HasIndex || !Mem.Index));
(MemKind == BDXMem || !Mem.Index) &&
(MemKind == BDLMem) == (Mem.Length != 0));
}
bool isMemDisp12(RegisterKind RegKind, bool HasIndex) const {
return isMem(RegKind, HasIndex) && inRange(Mem.Disp, 0, 0xfff);
bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
}
bool isMemDisp20(RegisterKind RegKind, bool HasIndex) const {
return isMem(RegKind, HasIndex) && inRange(Mem.Disp, -524288, 524287);
bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
}
bool isMemDisp12Len8(RegisterKind RegKind) const {
return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
}
// Override MCParsedAsmOperand.
@ -236,6 +251,13 @@ public:
addExpr(Inst, Mem.Disp);
Inst.addOperand(MCOperand::CreateReg(Mem.Index));
}
void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(Kind == KindMem && "Invalid operand type");
Inst.addOperand(MCOperand::CreateReg(Mem.Base));
addExpr(Inst, Mem.Disp);
addExpr(Inst, Mem.Length);
}
// Used by the TableGen code to check for particular operand types.
bool isGR32() const { return isReg(GR32Reg); }
@ -247,12 +269,13 @@ public:
bool isFP32() const { return isReg(FP32Reg); }
bool isFP64() const { return isReg(FP64Reg); }
bool isFP128() const { return isReg(FP128Reg); }
bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, false); }
bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, false); }
bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, false); }
bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, false); }
bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, true); }
bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, true); }
bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
bool isU4Imm() const { return isImm(0, 15); }
bool isU6Imm() const { return isImm(0, 63); }
bool isU8Imm() const { return isImm(0, 255); }
@ -288,19 +311,16 @@ private:
OperandMatchResultTy
parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
RegisterGroup Group, const unsigned *Regs,
SystemZOperand::RegisterKind Kind,
bool IsAddress = false);
RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
bool parseAddress(unsigned &Base, const MCExpr *&Disp,
unsigned &Index, const unsigned *Regs,
SystemZOperand::RegisterKind RegKind,
bool HasIndex);
unsigned &Index, const MCExpr *&Length,
const unsigned *Regs, RegisterKind RegKind);
OperandMatchResultTy
parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
const unsigned *Regs, SystemZOperand::RegisterKind RegKind,
bool HasIndex);
const unsigned *Regs, RegisterKind RegKind,
MemoryKind MemKind);
bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
StringRef Mnemonic);
@ -331,28 +351,23 @@ public:
// Used by the TableGen code to parse particular operand types.
OperandMatchResultTy
parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs,
SystemZOperand::GR32Reg);
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
}
OperandMatchResultTy
parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs,
SystemZOperand::GR64Reg);
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
}
OperandMatchResultTy
parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GR128Regs,
SystemZOperand::GR128Reg);
return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
}
OperandMatchResultTy
parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs,
SystemZOperand::ADDR32Reg, true);
return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
}
OperandMatchResultTy
parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs,
SystemZOperand::ADDR64Reg, true);
return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
}
OperandMatchResultTy
parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
@ -360,33 +375,31 @@ public:
}
OperandMatchResultTy
parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegFP, SystemZMC::FP32Regs,
SystemZOperand::FP32Reg);
return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
}
OperandMatchResultTy
parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegFP, SystemZMC::FP64Regs,
SystemZOperand::FP64Reg);
return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
}
OperandMatchResultTy
parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegister(Operands, RegFP, SystemZMC::FP128Regs,
SystemZOperand::FP128Reg);
return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
}
OperandMatchResultTy
parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseAddress(Operands, SystemZMC::GR32Regs,
SystemZOperand::ADDR32Reg, false);
return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
}
OperandMatchResultTy
parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseAddress(Operands, SystemZMC::GR64Regs,
SystemZOperand::ADDR64Reg, false);
return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
}
OperandMatchResultTy
parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseAddress(Operands, SystemZMC::GR64Regs,
SystemZOperand::ADDR64Reg, true);
return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
}
OperandMatchResultTy
parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
}
OperandMatchResultTy
parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@ -474,12 +487,12 @@ bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
SystemZAsmParser::OperandMatchResultTy
SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
RegisterGroup Group, const unsigned *Regs,
SystemZOperand::RegisterKind Kind,
bool IsAddress) {
RegisterKind Kind) {
if (Parser.getTok().isNot(AsmToken::Percent))
return MatchOperand_NoMatch;
Register Reg;
bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
if (parseRegister(Reg, Group, Regs, IsAddress))
return MatchOperand_ParseFail;
@ -488,14 +501,13 @@ SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
return MatchOperand_Success;
}
// Parse a memory operand into Base, Disp and Index. Regs maps asm
// register numbers to LLVM register numbers and RegKind says what kind
// of address register we're using (ADDR32Reg or ADDR64Reg). HasIndex
// says whether the address allows index registers.
// Parse a memory operand into Base, Disp, Index and Length.
// Regs maps asm register numbers to LLVM register numbers and RegKind
// says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
unsigned &Index, const unsigned *Regs,
SystemZOperand::RegisterKind RegKind,
bool HasIndex) {
unsigned &Index, const MCExpr *&Length,
const unsigned *Regs,
RegisterKind RegKind) {
// Parse the displacement, which must always be present.
if (getParser().parseExpression(Disp))
return true;
@ -503,27 +515,33 @@ bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
// Parse the optional base and index.
Index = 0;
Base = 0;
Length = 0;
if (getLexer().is(AsmToken::LParen)) {
Parser.Lex();
// Parse the first register.
Register Reg;
if (parseRegister(Reg, RegGR, Regs, RegKind))
return true;
// Check whether there's a second register. If so, the one that we
// just parsed was the index.
if (getLexer().is(AsmToken::Comma)) {
Parser.Lex();
if (!HasIndex)
return Error(Reg.StartLoc, "invalid use of indexed addressing");
Index = Reg.Num;
if (getLexer().is(AsmToken::Percent)) {
// Parse the first register and decide whether it's a base or an index.
Register Reg;
if (parseRegister(Reg, RegGR, Regs, RegKind))
return true;
if (getLexer().is(AsmToken::Comma))
Index = Reg.Num;
else
Base = Reg.Num;
} else {
// Parse the length.
if (getParser().parseExpression(Length))
return true;
}
// Check whether there's a second register. It's the base if so.
if (getLexer().is(AsmToken::Comma)) {
Parser.Lex();
Register Reg;
if (parseRegister(Reg, RegGR, Regs, RegKind))
return true;
Base = Reg.Num;
}
Base = Reg.Num;
// Consume the closing bracket.
if (getLexer().isNot(AsmToken::RParen))
@ -537,19 +555,37 @@ bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
// are as above.
SystemZAsmParser::OperandMatchResultTy
SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
const unsigned *Regs,
SystemZOperand::RegisterKind RegKind,
bool HasIndex) {
const unsigned *Regs, RegisterKind RegKind,
MemoryKind MemKind) {
SMLoc StartLoc = Parser.getTok().getLoc();
unsigned Base, Index;
const MCExpr *Disp;
if (parseAddress(Base, Disp, Index, Regs, RegKind, HasIndex))
const MCExpr *Length;
if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
return MatchOperand_ParseFail;
if (Index && MemKind != BDXMem)
{
Error(StartLoc, "invalid use of indexed addressing");
return MatchOperand_ParseFail;
}
if (Length && MemKind != BDLMem)
{
Error(StartLoc, "invalid use of length addressing");
return MatchOperand_ParseFail;
}
if (!Length && MemKind == BDLMem)
{
Error(StartLoc, "missing length in address");
return MatchOperand_ParseFail;
}
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
StartLoc, EndLoc));
Length, StartLoc, EndLoc));
return MatchOperand_Success;
}
@ -639,14 +675,13 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
// so we treat any plain expression as an immediate.
SMLoc StartLoc = Parser.getTok().getLoc();
unsigned Base, Index;
const MCExpr *Expr;
if (parseAddress(Base, Expr, Index, SystemZMC::GR64Regs,
SystemZOperand::ADDR64Reg, true))
const MCExpr *Expr, *Length;
if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
return true;
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
if (Base || Index)
if (Base || Index || Length)
Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
else
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));

19
lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
View File

@ -226,6 +226,18 @@ static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
return MCDisassembler::Success;
}
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
const unsigned *Regs) {
uint64_t Length = Field >> 16;
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Length < 256 && "Invalid BDLAddr12Len8");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(Disp));
Inst.addOperand(MCOperand::CreateImm(Length + 1));
return MCDisassembler::Success;
}
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
uint64_t Address,
const void *Decoder) {
@ -262,6 +274,13 @@ static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
}
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst,
uint64_t Field,
uint64_t Address,
const void *Decoder) {
return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
}
#include "SystemZGenDisassemblerTables.inc"
DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

11
lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp
View File

@ -154,6 +154,17 @@ void SystemZInstPrinter::printBDXAddrOperand(const MCInst *MI, int OpNum,
MI->getOperand(OpNum + 2).getReg(), O);
}
void SystemZInstPrinter::printBDLAddrOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
unsigned Base = MI->getOperand(OpNum).getReg();
uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
uint64_t Length = MI->getOperand(OpNum + 2).getImm();
O << Disp << '(' << Length;
if (Base)
O << ",%" << getRegisterName(Base);
O << ')';
}
void SystemZInstPrinter::printCond4Operand(const MCInst *MI, int OpNum,
raw_ostream &O) {
static const char *const CondNames[] = {

1
lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h
View File

@ -48,6 +48,7 @@ private:
void printOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);

14
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -49,7 +49,7 @@ private:
SmallVectorImpl<MCFixup> &Fixups) const;
// Called by the TableGen code to get the binary encoding of an address.
// The index, if any, is encoded first, followed by the base,
// The index or length, if any, is encoded first, followed by the base,
// followed by the displacement. In a 20-bit displacement,
// the low 12 bits are encoded before the high 8 bits.
uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
@ -60,6 +60,8 @@ private:
SmallVectorImpl<MCFixup> &Fixups) const;
uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const;
uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const;
// Operand OpNum of MI needs a PC-relative fixup of kind Kind at
// Offset bytes from the start of MI. Add the fixup to Fixups
@ -157,6 +159,16 @@ getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
| ((Disp & 0xff000) >> 12);
}
uint64_t SystemZMCCodeEmitter::
getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1;
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
return (Len << 16) | (Base << 12) | Disp;
}
uint64_t
SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,

13
lib/Target/SystemZ/SystemZInstrFormats.td
View File

@ -383,6 +383,19 @@ class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Has20BitOffset = 1;
}
class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<24> BDL1;
bits<16> BD2;
let Inst{47-40} = op;
let Inst{39-16} = BDL1;
let Inst{15-0} = BD2;
}
//===----------------------------------------------------------------------===//
// Instruction definitions with semantics
//===----------------------------------------------------------------------===//

6
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -282,6 +282,12 @@ def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
// Memory-to-memory moves.
let mayLoad = 1, mayStore = 1 in
def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1,
bdaddr12only:$BD2),
"mvc\t$BDL1, $BD2", []>;
//===----------------------------------------------------------------------===//
// Sign extensions
//===----------------------------------------------------------------------===//

100
lib/Target/SystemZ/SystemZOperands.td
View File

@ -53,49 +53,63 @@ class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
// Constructs an AsmOperandClass for addressing mode FORMAT, treating the
// registers as having BITSIZE bits and displacements as having DISPSIZE bits.
class AddressAsmOperand<string format, string bitsize, string dispsize>
// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
// is "".
class AddressAsmOperand<string format, string bitsize, string dispsize,
string length = "">
: AsmOperandClass {
let Name = format##bitsize##"Disp"##dispsize;
let Name = format##bitsize##"Disp"##dispsize##length;
let ParserMethod = "parse"##format##bitsize;
let RenderMethod = "add"##format##"Operands";
}
// Constructs both a DAG pattern and instruction operand for an addressing mode.
// The mode is selected by custom code in select<TYPE><DISPSIZE><SUFFIX>(),
// encoded by custom code in get<FORMAT><DISPSIZE>Encoding() and decoded
// by custom code in decode<TYPE><BITSIZE>Disp<DISPSIZE>Operand().
// The address registers have BITSIZE bits and displacements have
// DISPSIZE bits. NUMOPS is the number of operands that make up an
// address and OPERANDS lists the types of those operands using (ops ...).
// FORMAT is the type of addressing mode, which needs to match the names
// used in AddressAsmOperand.
class AddressingMode<string type, string bitsize, string dispsize,
string suffix, int numops, string format, dag operands>
// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands
// (base register, displacement, etc.). SELTYPE is the type of the memory
// operand for selection purposes; sometimes we want different selection
// choices for the same underlying addressing mode. SUFFIX is similarly
// a suffix appended to the displacement for selection purposes;
// e.g. we want to reject small 20-bit displacements if a 12-bit form
// also exists, but we want to accept them otherwise.
class AddressingMode<string seltype, string bitsize, string dispsize,
string suffix, string length, int numops, string format,
dag operands>
: ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
"select"##type##dispsize##suffix,
"select"##seltype##dispsize##suffix##length,
[add, sub, or, frameindex, z_adjdynalloc]>,
Operand<!cast<ValueType>("i"##bitsize)> {
let PrintMethod = "print"##format##"Operand";
let EncoderMethod = "get"##format##dispsize##"Encoding";
let DecoderMethod = "decode"##format##bitsize##"Disp"##dispsize##"Operand";
let EncoderMethod = "get"##format##dispsize##length##"Encoding";
let DecoderMethod =
"decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
let MIOperandInfo = operands;
let ParserMatchClass =
!cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize);
!cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
}
// An addressing mode with a base and displacement but no index.
class BDMode<string type, string bitsize, string dispsize, string suffix>
: AddressingMode<type, bitsize, dispsize, suffix, 2, "BDAddr",
: AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
(ops !cast<RegisterOperand>("ADDR"##bitsize),
!cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
// An addressing mode with a base, displacement and index.
class BDXMode<string type, string bitsize, string dispsize, string suffix>
: AddressingMode<type, bitsize, dispsize, suffix, 3, "BDXAddr",
: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
(ops !cast<RegisterOperand>("ADDR"##bitsize),
!cast<Immediate>("disp"##dispsize##"imm"##bitsize),
!cast<RegisterOperand>("ADDR"##bitsize))>;
// A BDMode paired with an immediate length operand of LENSIZE bits.
class BDLMode<string type, string bitsize, string dispsize, string suffix,
string lensize>
: AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
"BDLAddr",
(ops !cast<RegisterOperand>("ADDR"##bitsize),
!cast<Immediate>("disp"##dispsize##"imm"##bitsize),
!cast<Immediate>("imm"##bitsize))>;
//===----------------------------------------------------------------------===//
// Extracting immediate operands from nodes
// These all create MVT::i64 nodes to ensure the value is not sign-extended
@ -402,15 +416,16 @@ def disp12imm64 : Operand<i64>;
def disp20imm32 : Operand<i32>;
def disp20imm64 : Operand<i64>;
def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
// DAG patterns and operands for addressing modes. Each mode has
// the form <type><range><group> where:
// the form <type><range><group>[<len>] where:
//
// <type> is one of:
// shift : base + displacement (32-bit)
@ -418,6 +433,7 @@ def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
// bdxaddr : base + displacement + index
// laaddr : like bdxaddr, but used for Load Address operations
// dynalloc : base + displacement + index + ADJDYNALLOC
// bdladdr : base + displacement with a length field
//
// <range> is one of:
// 12 : the displacement is an unsigned 12-bit value
@ -428,20 +444,26 @@ def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
// range value (12 or 20)
// only : used when there is no equivalent instruction with the opposite
// range value
def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
//
// <len> is one of:
//
// <empty> : there is no length field
// len8 : the length field is 8 bits, with a range of [1, 0x100].
def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">;
//===----------------------------------------------------------------------===//
// Miscellaneous

44
test/MC/SystemZ/insn-bad.s
View File

@ -1730,6 +1730,50 @@
msy %r0, -524289
msy %r0, 524288
#CHECK: error: missing length in address
#CHECK: mvc 0, 0
#CHECK: error: missing length in address
#CHECK: mvc 0(%r1), 0(%r1)
#CHECK: error: invalid use of length addressing
#CHECK: mvc 0(1,%r1), 0(2,%r1)
#CHECK: error: invalid operand
#CHECK: mvc 0(0,%r1), 0(%r1)
#CHECK: error: invalid operand
#CHECK: mvc 0(257,%r1), 0(%r1)
#CHECK: error: invalid operand
#CHECK: mvc -1(1,%r1), 0(%r1)
#CHECK: error: invalid operand
#CHECK: mvc 4096(1,%r1), 0(%r1)
#CHECK: error: invalid operand
#CHECK: mvc 0(1,%r1), -1(%r1)
#CHECK: error: invalid operand
#CHECK: mvc 0(1,%r1), 4096(%r1)
#CHECK: error: %r0 used in an address
#CHECK: mvc 0(1,%r0), 0(%r1)
#CHECK: error: %r0 used in an address
#CHECK: mvc 0(1,%r1), 0(%r0)
#CHECK: error: invalid use of indexed addressing
#CHECK: mvc 0(%r1,%r2), 0(%r1)
#CHECK: error: invalid use of indexed addressing
#CHECK: mvc 0(1,%r2), 0(%r1,%r2)
#CHECK: error: unknown token in expression
#CHECK: mvc 0(-), 0
mvc 0, 0
mvc 0(%r1), 0(%r1)
mvc 0(1,%r1), 0(2,%r1)
mvc 0(0,%r1), 0(%r1)
mvc 0(257,%r1), 0(%r1)
mvc -1(1,%r1), 0(%r1)
mvc 4096(1,%r1), 0(%r1)
mvc 0(1,%r1), -1(%r1)
mvc 0(1,%r1), 4096(%r1)
mvc 0(1,%r0), 0(%r1)
mvc 0(1,%r1), 0(%r0)
mvc 0(%r1,%r2), 0(%r1)
mvc 0(1,%r2), 0(%r1,%r2)
mvc 0(-), 0
#CHECK: error: invalid operand
#CHECK: mvghi -1, 0
#CHECK: error: invalid operand

26
test/MC/SystemZ/insn-good.s
View File

@ -5313,6 +5313,32 @@
msy %r0, 524287(%r15,%r1)
msy %r15, 0
#CHECK: mvc 0(1), 0 # encoding: [0xd2,0x00,0x00,0x00,0x00,0x00]
#CHECK: mvc 0(1), 0(%r1) # encoding: [0xd2,0x00,0x00,0x00,0x10,0x00]
#CHECK: mvc 0(1), 0(%r15) # encoding: [0xd2,0x00,0x00,0x00,0xf0,0x00]
#CHECK: mvc 0(1), 4095 # encoding: [0xd2,0x00,0x00,0x00,0x0f,0xff]
#CHECK: mvc 0(1), 4095(%r1) # encoding: [0xd2,0x00,0x00,0x00,0x1f,0xff]
#CHECK: mvc 0(1), 4095(%r15) # encoding: [0xd2,0x00,0x00,0x00,0xff,0xff]
#CHECK: mvc 0(1,%r1), 0 # encoding: [0xd2,0x00,0x10,0x00,0x00,0x00]
#CHECK: mvc 0(1,%r15), 0 # encoding: [0xd2,0x00,0xf0,0x00,0x00,0x00]
#CHECK: mvc 4095(1,%r1), 0 # encoding: [0xd2,0x00,0x1f,0xff,0x00,0x00]
#CHECK: mvc 4095(1,%r15), 0 # encoding: [0xd2,0x00,0xff,0xff,0x00,0x00]
#CHECK: mvc 0(256,%r1), 0 # encoding: [0xd2,0xff,0x10,0x00,0x00,0x00]
#CHECK: mvc 0(256,%r15), 0 # encoding: [0xd2,0xff,0xf0,0x00,0x00,0x00]
mvc 0(1), 0
mvc 0(1), 0(%r1)
mvc 0(1), 0(%r15)
mvc 0(1), 4095
mvc 0(1), 4095(%r1)
mvc 0(1), 4095(%r15)
mvc 0(1,%r1), 0
mvc 0(1,%r15), 0
mvc 4095(1,%r1), 0
mvc 4095(1,%r15), 0
mvc 0(256,%r1), 0
mvc 0(256,%r15), 0
#CHECK: mvghi 0, 0 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00]
#CHECK: mvghi 4095, 0 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00]
#CHECK: mvghi 0, -32768 # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00]

15
test/MC/SystemZ/tokens.s
View File

@ -3,10 +3,16 @@
#CHECK: error: invalid instruction
#CHECK: foo 100, 200
#CHECK: error: register expected
#CHECK: error: unknown token in expression
#CHECK: foo 100(, 200
#CHECK: error: invalid instruction
#CHECK: foo 100(200), 300
#CHECK: error: register expected
#CHECK: foo 100(0), 200
#CHECK: foo 100(200,), 300
#CHECK: error: %r0 used in an address
#CHECK: foo 100(200,%r0), 300
#CHECK: error: invalid instruction
#CHECK: foo 100(200,%r1), 300
#CHECK: error: invalid operand
#CHECK: foo 100(%a0), 200
#CHECK: error: %r0 used in an address
@ -48,7 +54,10 @@
foo 100, 200
foo 100(, 200
foo 100(0), 200
foo 100(200), 300
foo 100(200,), 300
foo 100(200,%r0), 300
foo 100(200,%r1), 300
foo 100(%a0), 200
foo 100(%r0), 200
foo 100(%r1,%a0), 200