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Fix a dagcombine optimization. The optimization attempts to optimize a bitcast of fneg to integers

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by xoring the high-bit. This fails if the source operand is a vector because we need to negate
each of the elements in the vector.

Fix rdar://12281066 PR13813.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2012-09-13 14:54:28 +00:00
parent faf31d01db
commit 91a7e0184a
2 changed files with 23 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -5441,7 +5441,8 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
// This often reduces constant pool loads.
if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
(N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
N0.getNode()->hasOneUse() && VT.isInteger() &&
!VT.isVector() && !N0.getValueType().isVector()) {
SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
N0.getOperand(0));
AddToWorkList(NewConv.getNode());

21
test/CodeGen/X86/2012-09-13-dagco-fneg.ll Normal file
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@ -0,0 +1,21 @@
; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
; CHECK: foo
; Make sure we are not trying to use scalar xor on the high bits of the vector.
; CHECK-NOT: xorq
; CHECK: xorl
; CHECK-NEXT: ret
define i32 @foo() {
bb:
%tmp44.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, float 0.000000e+00>
%0 = bitcast <4 x float> %tmp44.i to i128
%1 = zext i128 %0 to i512
%2 = shl nuw nsw i512 %1, 256
%ins = or i512 %2, 3325764857622480139933400731976840738652108318779753826115024029985671937147149347761402413803120180680770390816681124225944317364750115981129923635970048
store i512 %ins, i512* undef, align 64
ret i32 0
}