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Pass i64 values correctly split in reg/mem to fastcc calls.

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This fixes fourinarow with -enable-x86-fastcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-05-14 12:03:10 +00:00
parent 239738a162
commit 920c0aa9c2
1 changed files with 1 additions and 2 deletions
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3
lib/Target/X86/X86ISelPattern.cpp
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@ -750,8 +750,7 @@ X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, Hi, PtrOff, DAG.getSrcValue(NULL)));
DAG.getSrcValue(NULL)));
ArgOffset += 4; ArgOffset += 4;
} }
break; break;