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fix some 80-col violations

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Gabor Greif 2008-08-30 10:09:02 +00:00
parent cd04708f59
commit 92362680c1
3 changed files with 7 additions and 4 deletions
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3
include/llvm/Target/TargetLowering.h
View File

@ -1089,7 +1089,8 @@ public:
(Ret.getOperand(0) == SDValue(Call.getNode(),1) ||
Ret.getOperand(0) == SDValue(Call.getNode(),0))) ||
(NumOps > 1 &&
Ret.getOperand(0) == SDValue(Call.getNode(),Call.getNode()->getNumValues()-1) &&
Ret.getOperand(0) == SDValue(Call.getNode(),
Call.getNode()->getNumValues()-1) &&
Ret.getOperand(1) == SDValue(Call.getNode(),0)))
return true;
return false;

6
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -359,7 +359,8 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
InFlag = Chain.getValue(1);
Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
Chain = CurDAG->getCopyToReg(Chain, IA64::B6,
targetEntryPoint, InFlag); // FLAG these?
InFlag = Chain.getValue(1);
CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
@ -520,7 +521,8 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(Tmp);
Tmp =
SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getTargetConstant(1, MVT::i64),
CurDAG->getTargetConstant(1,
MVT::i64),
Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}

2
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -398,7 +398,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
}
if(ValToConvert.getNode()) {
Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
}
}