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[mips] Don't cache IsO32 and IsFP64 in MipsTargetLowering::MipsCC

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Summary:
Use a MipsSubtarget reference instead.

No functional change.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5008

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-09-09 10:46:48 +00:00
parent 4faf24b6b7
commit 9242b13a4a
2 changed files with 28 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
lib/Target/Mips/MipsISelLowering.cpp
View File

@@ -2485,8 +2485,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
*DAG.getContext()); *DAG.getContext());
MipsCC::SpecialCallingConvType SpecialCallingConv = MipsCC::SpecialCallingConvType SpecialCallingConv =
getSpecialCallingConv(Callee); getSpecialCallingConv(Callee);
MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo, SpecialCallingConv);
CCInfo, SpecialCallingConv);
MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
Subtarget.abiUsesSoftFloat(), Subtarget.abiUsesSoftFloat(),
@@ -2687,8 +2686,7 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
*DAG.getContext()); *DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
CCInfo);
MipsCCInfo.analyzeCallResult(Ins, Subtarget.abiUsesSoftFloat(), MipsCCInfo.analyzeCallResult(Ins, Subtarget.abiUsesSoftFloat(),
CallNode, RetTy); CallNode, RetTy);
@@ -2735,8 +2733,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext()); *DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
CCInfo);
Function::const_arg_iterator FuncArg = Function::const_arg_iterator FuncArg =
DAG.getMachineFunction().getFunction()->arg_begin(); DAG.getMachineFunction().getFunction()->arg_begin();
bool UseSoftFloat = Subtarget.abiUsesSoftFloat(); bool UseSoftFloat = Subtarget.abiUsesSoftFloat();
@@ -2886,8 +2883,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
// CCState - Info about the registers and stack slot. // CCState - Info about the registers and stack slot.
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
CCInfo);
// Analyze return values. // Analyze return values.
MipsCCInfo.analyzeReturn(Outs, Subtarget.abiUsesSoftFloat(), MipsCCInfo.analyzeReturn(Outs, Subtarget.abiUsesSoftFloat(),
@@ -3397,10 +3393,10 @@ MipsTargetLowering::MipsCC::SpecialCallingConvType
} }
MipsTargetLowering::MipsCC::MipsCC( MipsTargetLowering::MipsCC::MipsCC(
CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, CallingConv::ID CC, const MipsSubtarget &Subtarget_, CCState &Info,
MipsCC::SpecialCallingConvType SpecialCallingConv_) MipsCC::SpecialCallingConvType SpecialCallingConv_)
: CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), : CCInfo(Info), CallConv(CC), Subtarget(Subtarget_),
SpecialCallingConv(SpecialCallingConv_){ SpecialCallingConv(SpecialCallingConv_) {
// Pre-allocate reserved argument area. // Pre-allocate reserved argument area.
CCInfo.AllocateStack(reservedArgArea(), 1); CCInfo.AllocateStack(reservedArgArea(), 1);
} }
@@ -3537,15 +3533,16 @@ void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
} }
unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); return Subtarget.isABI_O32() ? array_lengthof(O32IntRegs)
: array_lengthof(Mips64IntRegs);
} }
unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0;
} }
const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const { const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const {
return IsO32 ? O32IntRegs : Mips64IntRegs; return Subtarget.isABI_O32() ? O32IntRegs : Mips64IntRegs;
} }
llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
@@ -3554,15 +3551,19 @@ llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
if (SpecialCallingConv == Mips16RetHelperConv) if (SpecialCallingConv == Mips16RetHelperConv)
return CC_Mips16RetHelper; return CC_Mips16RetHelper;
return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; return Subtarget.isABI_O32()
? (Subtarget.isFP64bit() ? CC_MipsO32_FP64 : CC_MipsO32_FP32)
: CC_MipsN;
} }
llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; return Subtarget.isABI_O32()
? (Subtarget.isFP64bit() ? CC_MipsO32_FP64 : CC_MipsO32_FP32)
: CC_MipsN_VarArg;
} }
const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const { const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const {
return IsO32 ? O32IntRegs : Mips64DPRegs; return Subtarget.isABI_O32() ? O32IntRegs : Mips64DPRegs;
} }
void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
@@ -3591,7 +3592,7 @@ void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
const SDNode *CallNode, const SDNode *CallNode,
bool IsSoftFloat) const { bool IsSoftFloat) const {
if (IsSoftFloat || IsO32) if (IsSoftFloat || Subtarget.isABI_O32())
return VT; return VT;
// Check if the original type was fp128. // Check if the original type was fp128.
@@ -3603,6 +3604,10 @@ MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
return VT; return VT;
} }
unsigned MipsTargetLowering::MipsCC::regSize() const {
return Subtarget.isGP32bit() ? 4 : 8;
}
void MipsTargetLowering:: void MipsTargetLowering::
copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,

8
lib/Target/Mips/MipsISelLowering.h
View File

@@ -355,10 +355,10 @@ namespace llvm {
Mips16RetHelperConv, NoSpecialCallingConv Mips16RetHelperConv, NoSpecialCallingConv
}; };
MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info, MipsCC(CallingConv::ID CallConv, const MipsSubtarget &Subtarget,
CCState &Info,
SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
bool IsVarArg, bool IsSoftFloat, bool IsVarArg, bool IsSoftFloat,
const SDNode *CallNode, const SDNode *CallNode,
@@ -380,7 +380,7 @@ namespace llvm {
bool hasByValArg() const { return !ByValArgs.empty(); } bool hasByValArg() const { return !ByValArgs.empty(); }
/// regSize - Size (in number of bits) of integer registers. /// regSize - Size (in number of bits) of integer registers.
unsigned regSize() const { return IsO32 ? 4 : 8; } unsigned regSize() const;
/// numIntArgRegs - Number of integer registers available for calls. /// numIntArgRegs - Number of integer registers available for calls.
unsigned numIntArgRegs() const; unsigned numIntArgRegs() const;
@@ -429,7 +429,7 @@ namespace llvm {
CCState &CCInfo; CCState &CCInfo;
CallingConv::ID CallConv; CallingConv::ID CallConv;
bool IsO32, IsFP64; const MipsSubtarget &Subtarget;
SpecialCallingConvType SpecialCallingConv; SpecialCallingConvType SpecialCallingConv;
SmallVector<ByValArgInfo, 2> ByValArgs; SmallVector<ByValArgInfo, 2> ByValArgs;
}; };