6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-23 17:24:48 +00:00
Code Issues Projects Releases Wiki Activity

Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-06-05 19:08:58 +00:00
parent 6a784894b1
commit 925492279a
5 changed files with 14 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -64,7 +64,7 @@ namespace {
typedef SmallVector<MemOpQueueEntry,8> MemOpQueue; typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
typedef MemOpQueue::iterator MemOpQueueIter; typedef MemOpQueue::iterator MemOpQueueIter;
bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
int Offset, unsigned Base, bool BaseKill, int Opcode, int Offset, unsigned Base, bool BaseKill, int Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs); DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
@ -112,11 +112,11 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
return 0; return 0;
} }
/// mergeOps - Create and insert a LDM or STM with Base as base register and /// MergeOps - Create and insert a LDM or STM with Base as base register and
/// registers in Regs as the register operands that would be loaded / stored. /// registers in Regs as the register operands that would be loaded / stored.
/// It returns true if the transformation is done. /// It returns true if the transformation is done.
bool bool
ARMLoadStoreOpt::mergeOps(MachineBasicBlock &MBB, ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
int Offset, unsigned Base, bool BaseKill, int Offset, unsigned Base, bool BaseKill,
int Opcode, ARMCC::CondCodes Pred, int Opcode, ARMCC::CondCodes Pred,
@ -221,7 +221,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
PRegNum = RegNum; PRegNum = RegNum;
} else { } else {
// Can't merge this in. Try merge the earlier ones first. // Can't merge this in. Try merge the earlier ones first.
if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg, if (MergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg,
Scratch, dl, Regs)) { Scratch, dl, Regs)) {
Merges.push_back(prior(Loc)); Merges.push_back(prior(Loc));
for (unsigned j = SIndex; j < i; ++j) { for (unsigned j = SIndex; j < i; ++j) {
@ -241,7 +241,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
} }
bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1; bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg, if (MergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg,
Scratch, dl, Regs)) { Scratch, dl, Regs)) {
Merges.push_back(prior(Loc)); Merges.push_back(prior(Loc));
for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) { for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {

10
lib/Target/ARM/ARMRegisterInfo.td
View File

@ -103,28 +103,28 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
let MethodBodies = [{ let MethodBodies = [{
// FP is R11, R9 is available. // FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = { static const unsigned ARM_GPR_AO_1[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R12,ARM::LR, ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R8, ARM::R9, ARM::R10,
ARM::R11 }; ARM::R11 };
// FP is R11, R9 is not available. // FP is R11, R9 is not available.
static const unsigned ARM_GPR_AO_2[] = { static const unsigned ARM_GPR_AO_2[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R12,ARM::LR, ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R10, ARM::R8, ARM::R10,
ARM::R11 }; ARM::R11 };
// FP is R7, R9 is available. // FP is R7, R9 is available.
static const unsigned ARM_GPR_AO_3[] = { static const unsigned ARM_GPR_AO_3[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R12,ARM::LR, ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R4, ARM::R5, ARM::R6,
ARM::R8, ARM::R9, ARM::R10,ARM::R11, ARM::R8, ARM::R9, ARM::R10,ARM::R11,
ARM::R7 }; ARM::R7 };
// FP is R7, R9 is not available. // FP is R7, R9 is not available.
static const unsigned ARM_GPR_AO_4[] = { static const unsigned ARM_GPR_AO_4[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R12,ARM::LR, ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R4, ARM::R5, ARM::R6,
ARM::R8, ARM::R10,ARM::R11, ARM::R8, ARM::R10,ARM::R11,
@ -186,7 +186,7 @@ def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
// scavenging. // scavenging.
let MethodBodies = [{ let MethodBodies = [{
static const unsigned THUMB_tGPR_AO[] = { static const unsigned THUMB_tGPR_AO[] = {
ARM::R2, ARM::R1, ARM::R0, ARM::R0, ARM::R1, ARM::R2,
ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
// FP is R7, only low registers available. // FP is R7, only low registers available.

2
test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 184 ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 164
%"struct.Adv5::Ekin<3>" = type <{ i8 }> %"struct.Adv5::Ekin<3>" = type <{ i8 }>
%"struct.Adv5::X::Energyflux<3>" = type { double } %"struct.Adv5::X::Energyflux<3>" = type { double }

2
test/CodeGen/ARM/lsr-scale-addr-mode.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=arm | grep -F {str r2, \[r0, +r3, lsl #2\]} ; RUN: llvm-as < %s | llc -march=arm | grep lsl | grep -F {lsl #2\]}
; Should use scaled addressing mode. ; Should use scaled addressing mode.
define void @sintzero(i32* %a) nounwind { define void @sintzero(i32* %a) nounwind {

6
test/CodeGen/ARM/memcpy-inline.ll
View File

@ -1,9 +1,7 @@
; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldmia
; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep stmia
; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrb ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrb
; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrh ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrh
; This used to look for ldmia. But it's no longer lucky enough to
; have the load / store instructions lined up just right after
; scheduler change for pr3457. We'll look for a robust solution
; later.
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
@src = external global %struct.x @src = external global %struct.x