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Thumb2 prefer ADD register encoding T2 to T3 when possible.
rdar://10529664 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5238,6 +5238,26 @@ processInstruction(MCInst &Inst,
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return true;
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}
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break;
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case ARM::t2ADDrr: {
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// If the destination and first source operand are the same, and
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// there's no setting of the flags, use encoding T2 instead of T3.
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// Note that this is only for ADD, not SUB. This mirrors the system
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// 'as' behaviour. Make sure the wide encoding wasn't explicit.
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if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
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Inst.getOperand(5).getReg() != 0 ||
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(static_cast<ARMOperand*>(Operands[2])->isToken() &&
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static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
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break;
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tADDhirr);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(2));
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TmpInst.addOperand(Inst.getOperand(3));
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::tB:
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// A Thumb conditional branch outside of an IT block is a tBcc.
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if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
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