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When pattern matching during instruction selection make sure shl x,1 is not

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converted to add x,x if x is a undef.  add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2011-06-14 22:29:10 +00:00
parent 1c61990b2d
commit 92bcd96bbc
2 changed files with 56 additions and 0 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -3030,6 +3030,9 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// fold (shl x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
// fold (shl undef, x) -> 0
if (N0.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
// if (shl x, c) is known to be zero, return 0
if (DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(OpSizeInBits)))