Have legalize take care of DYNAMIC_STACKALLOC for us, implement llvm.stacksave/stackrestore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25332 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-15 08:55:25 +00:00
parent 903d278a9b
commit 934ea49a55
2 changed files with 8 additions and 36 deletions

View File

@ -136,8 +136,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
// V8 has no intrinsics for these particular operations.
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
@ -163,9 +161,12 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
// Not implemented yet.
// Expand these to their default code.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setStackPointerRegisterToSaveRestore(V8::O6);
computeRegisterProperties();
}
@ -701,21 +702,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(CC, MVT::i32), CompareFlag);
}
case ISD::DYNAMIC_STACKALLOC: {
SDOperand Chain = Op.getOperand(0);
SDOperand Size = Op.getOperand(1);
SDOperand SP = DAG.getCopyFromReg(Chain, V8::O6, MVT::i32);
Chain = SP.getValue(1);
SDOperand Res = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);
Chain = DAG.getCopyToReg(Chain, V8::O6, Res);
std::vector<MVT::ValueType> VTs(Op.Val->value_begin(), Op.Val->value_end());
std::vector<SDOperand> Ops;
Ops.push_back(Res);
Ops.push_back(Chain);
return DAG.getNode(ISD::MERGE_VALUES, VTs, Ops);
}
}
}

View File

@ -136,8 +136,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
// V8 has no intrinsics for these particular operations.
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
@ -163,9 +161,12 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
// Not implemented yet.
// Expand these to their default code.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setStackPointerRegisterToSaveRestore(V8::O6);
computeRegisterProperties();
}
@ -701,21 +702,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(CC, MVT::i32), CompareFlag);
}
case ISD::DYNAMIC_STACKALLOC: {
SDOperand Chain = Op.getOperand(0);
SDOperand Size = Op.getOperand(1);
SDOperand SP = DAG.getCopyFromReg(Chain, V8::O6, MVT::i32);
Chain = SP.getValue(1);
SDOperand Res = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);
Chain = DAG.getCopyToReg(Chain, V8::O6, Res);
std::vector<MVT::ValueType> VTs(Op.Val->value_begin(), Op.Val->value_end());
std::vector<SDOperand> Ops;
Ops.push_back(Res);
Ops.push_back(Chain);
return DAG.getNode(ISD::MERGE_VALUES, VTs, Ops);
}
}
}