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Handle lshr for i128 correctly on SPU also when

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shiftamount > 7.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120288 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-11-29 14:44:28 +00:00
parent c2ebfd454c
commit 9363f739cd
2 changed files with 19 additions and 4 deletions
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5
lib/Target/CellSPU/SPUInstrInfo.td
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@ -2727,6 +2727,8 @@ multiclass RotateMaskQuadByBitCount
def v8i16: ROTQMBYBIVecInst<v8i16>; def v8i16: ROTQMBYBIVecInst<v8i16>;
def v4i32: ROTQMBYBIVecInst<v4i32>; def v4i32: ROTQMBYBIVecInst<v4i32>;
def v2i64: ROTQMBYBIVecInst<v2i64>; def v2i64: ROTQMBYBIVecInst<v2i64>;
def r128: ROTQMBYBIInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
[/*no pattern*/]>;
} }
defm ROTQMBYBI: RotateMaskQuadByBitCount; defm ROTQMBYBI: RotateMaskQuadByBitCount;
@ -2762,7 +2764,8 @@ multiclass RotateMaskQuadByBits
defm ROTQMBI: RotateMaskQuadByBits; defm ROTQMBI: RotateMaskQuadByBits;
def : Pat<(srl GPRC:$rA, R32C:$rB), def : Pat<(srl GPRC:$rA, R32C:$rB),
(ROTQMBIr128 GPRC:$rA, (ROTQMBYBIr128 (ROTQMBIr128 GPRC:$rA,
(SFIr32 R32C:$rB, 0)),
(SFIr32 R32C:$rB, 0))>; (SFIr32 R32C:$rB, 0))>;

16
test/CodeGen/CellSPU/shift_ops.ll
View File

@ -10,11 +10,12 @@
; RUN: grep {rotqmbyi } %t1.s | count 1 ; RUN: grep {rotqmbyi } %t1.s | count 1
; RUN: grep {rotqmbii } %t1.s | count 2 ; RUN: grep {rotqmbii } %t1.s | count 2
; RUN: grep {rotqmby } %t1.s | count 1 ; RUN: grep {rotqmby } %t1.s | count 1
; RUN: grep {rotqmbi } %t1.s | count 1 ; RUN: grep {rotqmbi } %t1.s | count 2
; RUN: grep {rotqbyi } %t1.s | count 1 ; RUN: grep {rotqbyi } %t1.s | count 1
; RUN: grep {rotqbii } %t1.s | count 2 ; RUN: grep {rotqbii } %t1.s | count 2
; RUN: grep {rotqbybi } %t1.s | count 1 ; RUN: grep {rotqbybi } %t1.s | count 1
; RUN: grep {sfi } %t1.s | count 3 ; RUN: grep {sfi } %t1.s | count 4
; RUN: cat %t1.s | FileCheck %s
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu" target triple = "spu"
@ -281,3 +282,14 @@ define i32 @hi32_i64(i64 %arg) {
%2 = trunc i64 %1 to i32 %2 = trunc i64 %1 to i32
ret i32 %2 ret i32 %2
} }
; some random tests
define i128 @test_lshr_i128( i128 %val ) {
;CHECK: test_lshr_i128
;CHECK: sfi
;CHECK: rotqmbi
;CHECK: rotqmbybi
;CHECK: bi $lr
%rv = lshr i128 %val, 64
ret i128 %rv
}