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Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2013-10-05 05:38:16 +00:00
parent e8bcb9dd99
commit 936910d929
6 changed files with 75 additions and 1 deletions
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7
utils/TableGen/DAGISelMatcherEmitter.cpp
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@@ -242,6 +242,12 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx,
<< cast<CheckSameMatcher>(N)->getMatchNumber() << ",\n";
return 2;
case Matcher::CheckChildSame:
OS << "OPC_CheckChild"
<< cast<CheckChildSameMatcher>(N)->getChildNo() << "Same, "
<< cast<CheckChildSameMatcher>(N)->getMatchNumber() << ",\n";
return 2;
case Matcher::CheckPatternPredicate: {
StringRef Pred =cast<CheckPatternPredicateMatcher>(N)->getPredicate();
OS << "OPC_CheckPatternPredicate, " << getPatternPredicate(Pred) << ',';
@@ -753,6 +759,7 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M,
case Matcher::MoveChild: OS << "OPC_MoveChild"; break;
case Matcher::MoveParent: OS << "OPC_MoveParent"; break;
case Matcher::CheckSame: OS << "OPC_CheckSame"; break;
case Matcher::CheckChildSame: OS << "OPC_CheckChildSame"; break;
case Matcher::CheckPatternPredicate:
OS << "OPC_CheckPatternPredicate"; break;
case Matcher::CheckPredicate: OS << "OPC_CheckPredicate"; break;