mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[x86] Merge the remaining test cases into vector-blend.ll and remove all
the ISA-specific test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218818 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
406dccea99
commit
93803535ad
@ -1,11 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s
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define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
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; CHECK-LABEL: constant_pblendvb_avx2:
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; CHECK: vmovdqa
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; CHECK: vpblendvb
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%1 = select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <32 x i8> %xyzw, <32 x i8> %abcd
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ret <32 x i8> %1
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}
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declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>)
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@ -1,57 +0,0 @@
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; RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse4.1 | FileCheck %s
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; CHECK-LABEL: vsel_float
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NOT: orps
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; CHECK: ret
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define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
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%A = load <4 x float>* %v1
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%B = load <4 x float>* %v2
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%vsel = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %A, <4 x float> %B
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store <4 x float > %vsel, <4 x float>* %v1
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ret void
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}
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; CHECK-LABEL: vsel_i32
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NOT: orps
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; CHECK: ret
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define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
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%A = load <4 x i32>* %v1
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%B = load <4 x i32>* %v2
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B
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store <4 x i32 > %vsel, <4 x i32>* %v1
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ret void
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}
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK-LABEL: vsel_i64
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; CHECK: andnps
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; CHECK: orps
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; CHECK: ret
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define void@vsel_i64(<2 x i64>* %v1, <2 x i64>* %v2) {
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%A = load <2 x i64>* %v1
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%B = load <2 x i64>* %v2
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %A, <2 x i64> %B
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store <2 x i64 > %vsel, <2 x i64>* %v1
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ret void
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}
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK-LABEL: vsel_double
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; CHECK: andnps
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; CHECK: orps
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; CHECK: ret
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define void@vsel_double(<2 x double>* %v1, <2 x double>* %v2) {
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%A = load <2 x double>* %v1
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%B = load <2 x double>* %v2
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %A, <2 x double> %B
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store <2 x double > %vsel, <2 x double>* %v1
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ret void
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}
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@ -1,150 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
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;CHECK-LABEL: vsel_float:
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;CHECK: blendps
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK-LABEL: vsel_4xi8:
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;CHECK: blendps
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;CHECK: ret
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v2
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ret <4 x i8> %vsel
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}
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;CHECK-LABEL: vsel_4xi16:
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;CHECK: blendps
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;CHECK: ret
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define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i16> %v1, <4 x i16> %v2
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ret <4 x i16> %vsel
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}
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;CHECK-LABEL: vsel_i32:
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;CHECK: blendps
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;CHECK: ret
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> %v1, <4 x i32> %v2
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ret <4 x i32> %vsel
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}
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;CHECK-LABEL: vsel_double:
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;CHECK: movsd
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;CHECK: ret
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define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %v1, <4 x double> %v2
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ret <4 x double> %vsel
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}
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;CHECK-LABEL: vsel_i64:
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;CHECK: movsd
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;CHECK: ret
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define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v1, <4 x i64> %v2
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ret <4 x i64> %vsel
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}
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;CHECK-LABEL: vsel_i8:
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;CHECK: pblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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%vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
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ret <16 x i8> %vsel
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}
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;; TEST blend + compares
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; CHECK: A
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define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
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; CHECK: cmplepd
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; CHECK: blendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %max
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}
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; CHECK: B
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define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
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; CHECK: cmpnlepd
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; CHECK: blendvpd
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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}
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; CHECK: float_crash
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define void @float_crash() nounwind {
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entry:
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%merge205vector_func.i = select <4 x i1> undef, <4 x double> undef, <4 x double> undef
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%extract214vector_func.i = extractelement <4 x double> %merge205vector_func.i, i32 0
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store double %extract214vector_func.i, double addrspace(1)* undef, align 8
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ret void
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}
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; If we can figure out a blend has a constant mask, we should emit the
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; blend instruction with an immediate mask
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define <2 x double> @constant_blendvpd(<2 x double> %xy, <2 x double> %ab) {
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; In this case, we emit a simple movss
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; CHECK-LABEL: constant_blendvpd
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; CHECK: movsd
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; CHECK: ret
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %xy, <2 x double> %ab
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ret <2 x double> %1
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}
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define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) {
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; CHECK-LABEL: constant_blendvps
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; CHECK-NOT: mov
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; CHECK: blendps $7
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; CHECK: ret
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %xyzw, <4 x float> %abcd
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ret <4 x float> %1
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}
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define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) {
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; CHECK-LABEL: constant_pblendvb:
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; CHECK: movaps
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; CHECK: pblendvb
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; CHECK: ret
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%1 = select <16 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <16 x i8> %xyzw, <16 x i8> %abcd
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ret <16 x i8> %1
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}
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declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
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declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>)
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declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>)
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;; 2 tests for shufflevectors that optimize to blend + immediate
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; CHECK-LABEL: @blend_shufflevector_4xfloat
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; CHECK: blendps $6, %xmm1, %xmm0
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; CHECK: ret
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define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) {
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%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
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ret <4 x float> %1
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}
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; CHECK-LABEL: @blend_shufflevector_8xi16
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; CHECK: pblendw $134, %xmm1, %xmm0
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; CHECK: ret
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define <8 x i16> @blend_shufflevector_8xi16(<8 x i16> %a, <8 x i16> %b) {
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%1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 15>
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ret <8 x i16> %1
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}
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; PR20648 - a blend of constants isn't really a blend; it's just a constant pool load.
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; CHECK-LABEL: @does_not_blend
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @does_not_blend() {
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%select = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %select
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}
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@ -49,6 +49,72 @@ define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
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ret <4 x float> %vsel
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}
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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; SSE2-LABEL: vsel_4xi8:
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; SSE2: ## BB#0:
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; SSE2-NEXT: andps {{.*}}, %xmm1
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; SSE2-NEXT: andps {{.*}}, %xmm0
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; SSE2-NEXT: orps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_4xi8:
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; SSSE3: ## BB#0:
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; SSSE3-NEXT: andps {{.*}}, %xmm1
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; SSSE3-NEXT: andps {{.*}}, %xmm0
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; SSSE3-NEXT: orps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: vsel_4xi8:
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; SSE41: ## BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: vsel_4xi8:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: vsel_4xi8:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
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; AVX2-NEXT: retq
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v2
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ret <4 x i8> %vsel
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}
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define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
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; SSE2-LABEL: vsel_4xi16:
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; SSE2: ## BB#0:
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; SSE2-NEXT: andps {{.*}}, %xmm1
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; SSE2-NEXT: andps {{.*}}, %xmm0
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; SSE2-NEXT: orps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_4xi16:
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; SSSE3: ## BB#0:
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; SSSE3-NEXT: andps {{.*}}, %xmm1
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; SSSE3-NEXT: andps {{.*}}, %xmm0
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; SSSE3-NEXT: orps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: vsel_4xi16:
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; SSE41: ## BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: vsel_4xi16:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: vsel_4xi16:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; AVX2-NEXT: retq
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i16> %v1, <4 x i16> %v2
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ret <4 x i16> %vsel
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}
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: vsel_i32:
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; SSE2: ## BB#0:
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@ -440,6 +506,57 @@ define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd)
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ret <8 x float> %1
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}
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define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
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; SSE2-LABEL: constant_pblendvb_avx2:
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; SSE2: ## BB#0:
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; SSE2-NEXT: movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
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; SSE2-NEXT: andps %xmm4, %xmm2
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; SSE2-NEXT: movaps {{.*#+}} xmm5 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
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; SSE2-NEXT: andps %xmm5, %xmm0
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; SSE2-NEXT: orps %xmm2, %xmm0
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; SSE2-NEXT: andps %xmm4, %xmm3
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; SSE2-NEXT: andps %xmm5, %xmm1
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; SSE2-NEXT: orps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: constant_pblendvb_avx2:
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; SSSE3: ## BB#0:
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; SSSE3-NEXT: movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
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; SSSE3-NEXT: andps %xmm4, %xmm2
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; SSSE3-NEXT: movaps {{.*#+}} xmm5 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
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; SSSE3-NEXT: andps %xmm5, %xmm0
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; SSSE3-NEXT: orps %xmm2, %xmm0
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; SSSE3-NEXT: andps %xmm4, %xmm3
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; SSSE3-NEXT: andps %xmm5, %xmm1
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; SSSE3-NEXT: orps %xmm3, %xmm1
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: constant_pblendvb_avx2:
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; SSE41: ## BB#0:
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; SSE41-NEXT: movdqa %xmm0, %xmm4
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; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
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; SSE41-NEXT: pblendvb %xmm4, %xmm2
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; SSE41-NEXT: pblendvb %xmm1, %xmm3
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: movdqa %xmm3, %xmm1
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: constant_pblendvb_avx2:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vandps {{.*}}, %ymm1, %ymm1
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; AVX1-NEXT: vandps {{.*}}, %ymm0, %ymm0
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; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
|
||||
; AVX2-LABEL: constant_pblendvb_avx2:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
|
||||
; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%1 = select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <32 x i8> %xyzw, <32 x i8> %abcd
|
||||
ret <32 x i8> %1
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
|
||||
declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user