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Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904.
Now there is no special treatment of instructions that redefine part of a super-register. Instead, the super-register is marked with <imp-use,kill> and <imp-def>. For instance, from LowerSubregs on ARM: subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5 subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def> subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6 subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78466 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -270,14 +270,15 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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MachineBasicBlock::iterator CopyMI = MI;
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--CopyMI;
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// INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
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if (!MI->getOperand(1).isUndef())
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
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// Transfer the kill/dead flags, if needed.
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if (MI->getOperand(0).isDead()) {
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TransferDeadFlag(MI, DstSubReg, TRI);
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// Also add a SrcReg<imp-kill> of the super register.
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
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} else if (MI->getOperand(1).isUndef()) {
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// If SrcReg was marked <undef> we must make sure it is alive after this
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// replacement. Add a SrcReg<imp-def> operand.
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} else {
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// Make sure the full DstReg is live after this replacement.
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
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}
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@@ -293,7 +294,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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DOUT << "\n";
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MBB->erase(MI);
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return true;
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return true;
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}
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/// runOnMachineFunction - Reduce subregister inserts and extracts to register
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