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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-03 18:32:50 +00:00
[x86] Fix signed relocations for i64i32imm operands
These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse
parent
fe7fa28084
commit
93f81d9b33
@ -395,20 +395,21 @@ namespace X86II {
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// This three-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmShift = REXShift + 1,
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ImmMask = 7 << ImmShift,
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ImmMask = 15 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm8PCRel = 2 << ImmShift,
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Imm16 = 3 << ImmShift,
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Imm16PCRel = 4 << ImmShift,
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Imm32 = 5 << ImmShift,
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Imm32PCRel = 6 << ImmShift,
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Imm64 = 7 << ImmShift,
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Imm32S = 7 << ImmShift,
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Imm64 = 8 << ImmShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = ImmShift + 3,
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FPTypeShift = ImmShift + 4,
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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@ -557,6 +558,7 @@ namespace X86II {
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case X86II::Imm16:
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case X86II::Imm16PCRel: return 2;
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case X86II::Imm32:
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case X86II::Imm32S:
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case X86II::Imm32PCRel: return 4;
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case X86II::Imm64: return 8;
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}
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@ -574,6 +576,25 @@ namespace X86II {
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case X86II::Imm8:
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case X86II::Imm16:
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case X86II::Imm32:
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case X86II::Imm32S:
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case X86II::Imm64:
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return false;
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}
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}
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/// isImmSigned - Return true if the immediate of the specified instruction's
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/// TSFlags indicates that it is signed.
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inline unsigned isImmSigned(uint64_t TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: llvm_unreachable("Unknown immediate signedness");
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case X86II::Imm32S:
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return true;
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case X86II::Imm8:
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case X86II::Imm8PCRel:
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case X86II::Imm16:
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case X86II::Imm16PCRel:
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case X86II::Imm32:
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case X86II::Imm32PCRel:
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case X86II::Imm64:
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return false;
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}
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@ -233,6 +233,12 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
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unsigned Size = X86II::getSizeOfImm(TSFlags);
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bool isPCRel = X86II::isImmPCRel(TSFlags);
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if (X86II::isImmSigned(TSFlags)) {
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switch (Size) {
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default: llvm_unreachable("Unsupported signed fixup size!");
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case 4: return MCFixupKind(X86::reloc_signed_4byte);
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}
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}
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return MCFixup::getKindForSize(Size, isPCRel);
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}
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@ -1566,17 +1572,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
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CurByte, OS, Fixups);
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} else {
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unsigned FixupKind;
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// FIXME: Is there a better way to know that we need a signed relocation?
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if (MI.getOpcode() == X86::ADD64ri32 ||
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MI.getOpcode() == X86::MOV64ri32 ||
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MI.getOpcode() == X86::MOV64mi32 ||
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MI.getOpcode() == X86::PUSH64i32)
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FixupKind = X86::reloc_signed_4byte;
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else
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FixupKind = getImmFixupKind(TSFlags);
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EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
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X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
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X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
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CurByte, OS, Fixups);
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}
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}
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@ -229,10 +229,10 @@ def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, i32immSExt8:$src2))],
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IIC_IMUL32_RRI>, OpSize16;
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def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt32:$src2))],
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IIC_IMUL64_RRI>;
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def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
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@ -272,10 +272,10 @@ def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
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(X86smul_flag (load addr:$src1),
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i32immSExt8:$src2))],
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IIC_IMUL32_RMI>, OpSize16;
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def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
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(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32
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(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i64immSExt32:$src2))],
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IIC_IMUL64_RMI>;
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@ -681,7 +681,7 @@ def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
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Imm32, i32imm, imm, i32i8imm, i32immSExt8,
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1, 0, 1, 0>;
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def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
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Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
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Imm32S, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
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1, 0, 0, 1>;
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/// ITy - This instruction base class takes the type info for the instruction.
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@ -61,8 +61,8 @@ def MRM_DF : Format<59>;
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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// machine code emitter.
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class ImmType<bits<3> val> {
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bits<3> Value = val;
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class ImmType<bits<4> val> {
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bits<4> Value = val;
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}
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def NoImm : ImmType<0>;
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def Imm8 : ImmType<1>;
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@ -71,7 +71,8 @@ def Imm16 : ImmType<3>;
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def Imm16PCRel : ImmType<4>;
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def Imm32 : ImmType<5>;
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def Imm32PCRel : ImmType<6>;
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def Imm64 : ImmType<7>;
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def Imm32S : ImmType<7>;
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def Imm64 : ImmType<8>;
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// FPFormat - This specifies what form this FP instruction has. This is used by
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// the Floating-Point stackifier pass.
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@ -232,29 +233,29 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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let TSFlags{8} = hasAdSizePrefix;
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let TSFlags{13-9} = Prefix;
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let TSFlags{14} = hasREX_WPrefix;
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let TSFlags{17-15} = ImmT.Value;
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let TSFlags{20-18} = FPForm.Value;
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let TSFlags{21} = hasLockPrefix;
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let TSFlags{23-22} = ExeDomain.Value;
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let TSFlags{31-24} = Opcode;
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let TSFlags{32} = hasVEXPrefix;
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let TSFlags{33} = hasVEX_WPrefix;
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let TSFlags{34} = hasVEX_4VPrefix;
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let TSFlags{35} = hasVEX_4VOp3Prefix;
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let TSFlags{36} = hasVEX_i8ImmReg;
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let TSFlags{37} = hasVEX_L;
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let TSFlags{38} = ignoresVEX_L;
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let TSFlags{39} = hasEVEXPrefix;
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let TSFlags{40} = hasEVEX_K;
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let TSFlags{41} = hasEVEX_Z;
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let TSFlags{42} = hasEVEX_L2;
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let TSFlags{43} = hasEVEX_B;
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let TSFlags{45-44} = EVEX_CD8E;
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let TSFlags{48-46} = EVEX_CD8V;
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let TSFlags{49} = has3DNow0F0FOpcode;
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let TSFlags{50} = hasMemOp4Prefix;
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let TSFlags{51} = hasXOP_Prefix;
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let TSFlags{52} = hasEVEX_RC;
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let TSFlags{18-15} = ImmT.Value;
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let TSFlags{21-19} = FPForm.Value;
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let TSFlags{22} = hasLockPrefix;
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let TSFlags{24-23} = ExeDomain.Value;
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let TSFlags{32-25} = Opcode;
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let TSFlags{33} = hasVEXPrefix;
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let TSFlags{34} = hasVEX_WPrefix;
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let TSFlags{35} = hasVEX_4VPrefix;
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let TSFlags{36} = hasVEX_4VOp3Prefix;
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let TSFlags{37} = hasVEX_i8ImmReg;
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let TSFlags{38} = hasVEX_L;
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let TSFlags{39} = ignoresVEX_L;
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let TSFlags{40} = hasEVEXPrefix;
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let TSFlags{41} = hasEVEX_K;
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let TSFlags{42} = hasEVEX_Z;
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let TSFlags{43} = hasEVEX_L2;
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let TSFlags{44} = hasEVEX_B;
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let TSFlags{46-45} = EVEX_CD8E;
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let TSFlags{49-47} = EVEX_CD8V;
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let TSFlags{50} = has3DNow0F0FOpcode;
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let TSFlags{51} = hasMemOp4Prefix;
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let TSFlags{52} = hasXOP_Prefix;
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let TSFlags{53} = hasEVEX_RC;
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}
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class PseudoI<dag oops, dag iops, list<dag> pattern>
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@ -294,6 +295,12 @@ class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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@ -743,6 +750,9 @@ class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
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class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
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class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
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class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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@ -1039,7 +1039,7 @@ def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
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def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
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"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
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Requires<[In64BitMode]>;
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def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
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def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
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"push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
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}
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@ -1208,9 +1208,9 @@ def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
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def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
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"movabs{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, imm:$src)], IIC_MOV>;
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def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
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def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
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}
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} // SchedRW
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@ -1224,9 +1224,9 @@ def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
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def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
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"mov{l}\t{$src, $dst|$dst, $src}",
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[(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
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def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
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def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
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} // SchedRW
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let hasSideEffects = 0 in {
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@ -2100,6 +2100,7 @@ multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
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defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
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int_x86_tbm_bextri_u32, i32imm, imm>;
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let ImmT = Imm32S in
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defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
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int_x86_tbm_bextri_u64, i64i32imm,
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i64immSExt32>, VEX_W;
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16
test/MC/X86/x86_64-signed-reloc.s
Normal file
16
test/MC/X86/x86_64-signed-reloc.s
Normal file
@ -0,0 +1,16 @@
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// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r | FileCheck %s
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// CHECK: Relocations [
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// CHECK-NEXT: Section ({{[0-9]+}}) .rela.text {
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pushq $foo // CHECK-NEXT: R_X86_64_32S
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addq $foo, %rax // CHECK-NEXT: R_X86_64_32S
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andq $foo, %rax // CHECK-NEXT: R_X86_64_32S
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movq $foo, %rax // CHECK-NEXT: R_X86_64_32S
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bextr $foo, (%edi), %eax // CHECK-NEXT: R_X86_64_32
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bextr $foo, (%rdi), %rax // CHECK-NEXT: R_X86_64_32S
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imul $foo, %rax // CHECK-NEXT: R_X86_64_32S
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// CHECK-NEXT: }
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// CHECK-NEXT: ]
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