From 93fa4766c21062c06a274d09169e15779c06603b Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Thu, 28 Jul 2011 01:26:50 +0000 Subject: [PATCH] Add patterns to generate copies for extract_subvector instead of using vextractf128. This will reduce the number of issued instruction for several avx codes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136323 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrSSE.td | 12 ++++++++++++ test/CodeGen/X86/avx-cast.ll | 6 +++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index a3e8c4065d4..db1ab527f4f 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -5452,6 +5452,18 @@ def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)), (v32i8 VR256:$src1), (EXTRACT_get_vextractf128_imm VR128:$ext)))>; +// Special COPY patterns +def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>; +def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>; + +def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>; +def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>; + + //===----------------------------------------------------------------------===// // VMASKMOV - Conditional SIMD Packed Loads and Stores // diff --git a/test/CodeGen/X86/avx-cast.ll b/test/CodeGen/X86/avx-cast.ll index 7e368b3d9ee..d6d2415ea05 100644 --- a/test/CodeGen/X86/avx-cast.ll +++ b/test/CodeGen/X86/avx-cast.ll @@ -24,21 +24,21 @@ entry: ret <4 x i64> %shuffle.i } -; CHECK: vextractf128 $0 +; CHECK-NOT: vextractf128 $0 define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp { entry: %shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> ret <4 x float> %shuffle.i } -; CHECK: vextractf128 $0 +; CHECK-NOT: vextractf128 $0 define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp { entry: %shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> ret <2 x i64> %shuffle.i } -; CHECK: vextractf128 $0 +; CHECK-NOT: vextractf128 $0 define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp { entry: %shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32>