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https://github.com/c64scene-ar/llvm-6502.git
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We no longer need to preprocess SparcV9.td before sending it through tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
7dff053540
commit
942e7230e5
@ -50,7 +50,7 @@ TABLEGEN_FILES := $(wildcard *.td)
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$(TARGET_NAME)CodeEmitter.inc.tmp: $(TABLEGEN_FILES) $(TBLGEN)
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@${ECHO} "TableGen-erating " $(TARGET_NAME)
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$(CC) -E -xc -P $(TARGET_NAME).td | $(TBLGEN) -gen-emitter -o $@
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$(TBLGEN) $(TARGET_NAME).td -gen-emitter -o $@
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$(TARGET_NAME)CodeEmitter.inc: $(TARGET_NAME)CodeEmitter.inc.tmp
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$(VERB) # Only copy over the real .inc file if it has changed!
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@ -2,9 +2,9 @@
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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#include "../Target.td"
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include "../Target.td"
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#include "SparcV9_Reg.td"
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include "SparcV9_Reg.td"
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -24,9 +24,9 @@ class InstV9 : Instruction { // Sparc instruction baseline
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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#include "SparcV9_F2.td"
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#include "SparcV9_F3.td"
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#include "SparcV9_F4.td"
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include "SparcV9_F2.td"
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include "SparcV9_F3.td"
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include "SparcV9_F4.td"
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//===----------------------------------------------------------------------===//
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// Instruction list...
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@ -54,7 +54,7 @@ set op2 = 0b011 in {
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// Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
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// The following deprecated instructions don't seem to play nice on Sparc
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#if 0
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/*
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set isDeprecated = 1 in {
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set op2 = 0b110 in {
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def FBA : F2_2<0b1000, "fba">; // Branch always
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@ -75,7 +75,7 @@ set isDeprecated = 1 in {
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def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
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}
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}
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#endif
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*/
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// We now make these same opcodes represent the FBPfcc instructions
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set op2 = 0b101 in {
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@ -99,7 +99,7 @@ set op2 = 0b101 in {
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// Section A.5: Branch on FP condition codes with prediction - p143
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// Not used in the Sparc backend (directly)
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#if 0
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/*
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set op2 = 0b101 in {
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def FBPA : F2_3<0b1000, "fba">; // Branch always
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def FBPN : F2_3<0b0000, "fbn">; // Branch never
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@ -118,10 +118,10 @@ set op2 = 0b101 in {
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def FBPULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
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def FBPO : F2_3<0b1111, "fbo">; // Branch on ordered
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}
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#endif
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*/
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// Section A.6: Branch on Integer condition codes (Bicc) - p146
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#if 0
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/*
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set isDeprecated = 1 in {
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set op2 = 0b010 in {
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def BA : F2_2<0b1000, "ba">; // Branch always
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@ -142,7 +142,7 @@ set isDeprecated = 1 in {
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def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
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}
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}
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#endif
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*/
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// Using the format of A.7 instructions...
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set op2 = 0b001 in {
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@ -168,7 +168,7 @@ set op2 = 0b001 in {
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// Section A.7: Branch on integer condition codes with prediction - p148
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// Not used in the Sparc backend
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#if 0
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/*
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set op2 = 0b001 in {
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def BPA : F2_3<0b1000, "bpa">; // Branch always
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def BPN : F2_3<0b0000, "bpn">; // Branch never
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@ -187,7 +187,7 @@ set op2 = 0b001 in {
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def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
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def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
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}
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#endif
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*/
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// Section A.8: CALL - p151, the only Format #1 instruction
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def CALL : InstV9 {
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@ -204,7 +204,7 @@ def CALL : InstV9 {
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// Section A.10: Divide (64-bit / 32-bit) - p178
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// Not used in the Sparc backend
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#if 0
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/*
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set isDeprecated = 1 in {
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def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
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def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
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@ -215,16 +215,16 @@ set isDeprecated = 1 in {
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def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
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def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
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}
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#endif
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*/
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// Section A.11: DONE and RETRY - p181
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// Not used in the Sparc backend
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#if 0
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/*
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set isPrivileged = 1 in {
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def DONE : F3_18<0, "done">; // done
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def RETRY : F3_18<1, "retry">; // retry
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}
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#endif
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*/
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// Section A.12: Floating-Point Add and Subtract - p156
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def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds frs1, frs2, frd
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@ -239,11 +239,11 @@ def FCMPS : F3_15<2, 0b110101, 0b001010001, "fcmps">; // fcmps %fcc, r1, r2
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def FCMPD : F3_15<2, 0b110101, 0b001010010, "fcmpd">; // fcmpd %fcc, r1, r2
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def FCMPQ : F3_15<2, 0b110101, 0b001010011, "fcmpq">; // fcmpq %fcc, r1, r2
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// Currently unused in the Sparc backend
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#if 0
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/*
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def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">; // fcmpes %fcc, r1, r2
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def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">; // fcmped %fcc, r1, r2
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def FCMPEQ : F3_15<2, 0b110101, 0b001010111, "fcmpeq">; // fcmpeq %fcc, r1, r2
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#endif
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*/
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// Section A.14: Convert floating-point to integer - p161
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def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">; // fstox rs2, rd
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@ -348,12 +348,12 @@ def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [rs1+rs2], rd
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def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [rs1+imm], rd
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def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [rs1+rs2], rd
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def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [rs1+imm], rd
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#if 0
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/*
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set isDeprecated = 1 in {
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def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [rs1+rs2], rd
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def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [rs1+imm], rd
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}
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#endif
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*/
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// Section A.31: Logical operations
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def ANDr : F3_1<2, 0b000001, "and">; // and rs1, rs2, rd
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@ -614,7 +614,7 @@ def UDIVXi : F3_2<2, 0b001101, "udivx">; // udivx r, i, r
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// Section A.38: Multiply (32-bit) - p200
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// Not used in the Sparc backend
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#if 0
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/*
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set Inst{13} = 0 in {
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def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
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def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
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@ -627,7 +627,7 @@ set Inst{13} = 1 in {
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def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
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def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
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}
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#endif
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*/
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// Section A.39: Multiply Step - p202
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// Not currently used in the Sparc backend
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@ -679,7 +679,7 @@ set op2 = 0b100 in {
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// Section A.49: Shift - p221
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// Not currently used in the Sparc backend
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#if 0
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/*
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uses 5 least significant bits of rs2
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set x = 0 in {
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def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
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@ -689,7 +689,7 @@ set x = 0 in {
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def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
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def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
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}
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#endif
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*/
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// uses 6 least significant bits of rs2
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set x = 0 in {
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@ -724,20 +724,20 @@ def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
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def STDFi : F3_2rd<3, 0b100111, "std">; // std r, [r+i]
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// Not currently used in the Sparc backend
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#if 0
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/*
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def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
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def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
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#endif
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*/
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// FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
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// while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
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// These are being disabled because they aren't used in the Sparc backend.
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#if 0
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/*
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set isDeprecated = 1 in {
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def STFSRr : F3_1<3, 0b100101, "st">; // st %fsr, [r+r]
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def STFSRi : F3_2<3, 0b100101, "st">; // st %fsr, [r+i]
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}
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#endif
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*/
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def STXFSRr : F3_1<3, 0b100101, "stx">; // stx %fsr, [r+r]
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def STXFSRi : F3_2<3, 0b100101, "stx">; // stx %fsr, [r+i]
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