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More ARM multiply instruction encoding information.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-22 17:16:17 +00:00
parent 8a116e0b3e
commit 9463d0e400
3 changed files with 63 additions and 34 deletions
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19
lib/Target/ARM/ARMInstrFormats.td
View File

@ -911,13 +911,26 @@ class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
}
// Most significant word multiply
class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
InstrItinClass itin, string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
opc, asm, "", pattern> {
let Inst{7-4} = 0b1001;
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{7-4} = opc7_4;
let Inst{20} = 1;
let Inst{27-21} = opcod;
let Inst{19-16} = Rd;
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
// MSW multiple w/ Ra operand
class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
InstrItinClass itin, string opc, string asm, list<dag> pattern>
: AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
bits<4> Ra;
let Inst{15-12} = Ra;
}
// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>

56
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2265,8 +2265,8 @@ class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
bits<4> RdHi;
bits<4> Rm;
bits<4> Rn;
let Inst{19-16} = RdLo;
let Inst{15-12} = RdHi;
let Inst{19-16} = RdHi;
let Inst{15-12} = RdLo;
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
@ -2333,49 +2333,43 @@ def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
} // neverHasSideEffects
// Most significant word multiply
def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMUL32, "smmul", "\t$dst, $a, $b",
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0001;
let Inst{15-12} = 0b1111;
}
def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMUL32, "smmulr", "\t$dst, $a, $b",
def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0011; // R = 1
let Inst{15-12} = 0b1111;
}
def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0001;
}
def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
Requires<[IsARM, HasV6]>;
def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c",
def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0011; // R = 1
}
Requires<[IsARM, HasV6]>;
def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b1101;
}
def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
Requires<[IsARM, HasV6]>;
def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c",
def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b1111; // R = 1
}
Requires<[IsARM, HasV6]>;
multiclass AI_smul<string opc, PatFrag opnode> {
def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),

22
test/MC/ARM/simple-encoding.ll
View File

@ -128,4 +128,26 @@ define i64 @f13() {
entry:
ret i64 9223372036854775807
}
define i32 @f14(i32 %x, i32 %y) {
; CHECK: f14:
; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7]
%tmp = sext i32 %x to i64
%tmp1 = sext i32 %y to i64
%tmp2 = mul i64 %tmp1, %tmp
%tmp3 = lshr i64 %tmp2, 32
%tmp3.upgrd.1 = trunc i64 %tmp3 to i32
ret i32 %tmp3.upgrd.1
}
define i32 @f15(i32 %x, i32 %y) {
; CHECK: f15:
; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0]
%tmp = zext i32 %x to i64
%tmp1 = zext i32 %y to i64
%tmp2 = mul i64 %tmp1, %tmp
%tmp3 = lshr i64 %tmp2, 32
%tmp3.upgrd.2 = trunc i64 %tmp3 to i32
ret i32 %tmp3.upgrd.2
}
declare void @llvm.trap() nounwind