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PPC: Mark vector CC action for SETO and SETONE as Expand

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Another bug found by llvm-stress! This fixes hitting
  llvm_unreachable("Invalid integer vector compare condition");
at the end of getVCmpInst in PPCISelDAGToDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185855 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-07-08 20:00:03 +00:00
parent e5a532dae3
commit 947d447ee0
2 changed files with 20 additions and 0 deletions
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3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -487,6 +487,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
}
if (Subtarget->has64BitSupport()) {

17
test/CodeGen/PowerPC/altivec-ord.ll Normal file
View File

@ -0,0 +1,17 @@
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu"
define <4 x i16> @test(<4 x float> %f, <4 x float> %g) {
entry:
%r = fcmp ord <4 x float> %f, %g
%s = sext <4 x i1> %r to <4 x i16>
ret <4 x i16> %s
}
define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) {
entry:
%r = fcmp one <4 x float> %f, %g
%s = sext <4 x i1> %r to <4 x i16>
ret <4 x i16> %s
}