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Initial implementation of MipsTargetLowering::isLegalAddressingMode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-11-17 00:25:41 +00:00
parent 8b149cbfc6
commit 94e472832f
3 changed files with 63 additions and 0 deletions
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20
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3482,6 +3482,26 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
}
bool
MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
switch (AM.Scale) {
case 0: // "r+i" or just "i", depending on HasBaseReg.
break;
case 1:
if (!AM.HasBaseReg) // allow "r+i".
break;
return false; // disallow "r+r" or "r+r+i".
default:
return false;
}
return true;
}
bool
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// The Mips target isn't yet aware of offsets.

2
lib/Target/Mips/MipsISelLowering.h
View File

@ -357,6 +357,8 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,

41
test/CodeGen/Mips/addressing-mode.ll Normal file
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@ -0,0 +1,41 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
; Check that LSR doesn't choose a solution with a formula "reg + 4*reg".
;
; CHECK: $BB0_2:
; CHECK-NOT: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
define i32 @f0(i32 %n, i32 %m, [256 x i32]* nocapture %a, [256 x i32]* nocapture %b) nounwind readonly {
entry:
br label %for.cond1.preheader
for.cond1.preheader:
%s.022 = phi i32 [ 0, %entry ], [ %add7, %for.inc9 ]
%i.021 = phi i32 [ 0, %entry ], [ %add10, %for.inc9 ]
br label %for.body3
for.body3:
%s.120 = phi i32 [ %s.022, %for.cond1.preheader ], [ %add7, %for.body3 ]
%j.019 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ]
%arrayidx4 = getelementptr inbounds [256 x i32]* %a, i32 %i.021, i32 %j.019
%0 = load i32* %arrayidx4, align 4
%arrayidx6 = getelementptr inbounds [256 x i32]* %b, i32 %i.021, i32 %j.019
%1 = load i32* %arrayidx6, align 4
%add = add i32 %0, %s.120
%add7 = add i32 %add, %1
%add8 = add nsw i32 %j.019, %m
%cmp2 = icmp slt i32 %add8, 64
br i1 %cmp2, label %for.body3, label %for.inc9
for.inc9:
%add10 = add nsw i32 %i.021, %n
%cmp = icmp slt i32 %add10, 64
br i1 %cmp, label %for.cond1.preheader, label %for.end11
for.end11:
ret i32 %add7
}