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Mark the SPU 'lr' instruction to never have side effects.

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This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila
2010-06-21 15:08:16 +00:00
parent 91fdee125c
commit 951b229ccf
5 changed files with 18 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/CellSPU/SPUInstrInfo.cpp
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@@ -164,11 +164,9 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(0).isReg() && MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() && MI.getOperand(1).isReg() &&
"invalid SPU OR<type>_<vec> or LR instruction!"); "invalid SPU OR<type>_<vec> or LR instruction!");
if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
sourceReg = MI.getOperand(1).getReg(); sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg(); destReg = MI.getOperand(0).getReg();
return true; return true;
}
break; break;
} }
case SPU::ORv16i8: case SPU::ORv16i8:

5
test/CodeGen/CellSPU/call.ll
View File

@@ -1,7 +1,8 @@
; RUN: llc < %s -march=cellspu > %t1.s ; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s
; RUN: grep brsl %t1.s | count 1 ; RUN: grep brsl %t1.s | count 1
; RUN: grep brasl %t1.s | count 1 ; RUN: grep brasl %t1.s | count 1
; RUN: grep stqd %t1.s | count 80 ; RUN: grep stqd %t1.s | count 80
; RUN: llc < %s -march=cellspu | FileCheck %s
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu" target triple = "spu"
@@ -16,6 +17,8 @@ entry:
declare void @extern_stub_1(i32, i32) declare void @extern_stub_1(i32, i32)
define i32 @stub_1(i32 %x, float %y) { define i32 @stub_1(i32 %x, float %y) {
; CHECK: il $3, 0
; CHECK: bi $lr
entry: entry:
ret i32 0 ret i32 0
} }

4
test/CodeGen/CellSPU/call_indirect.ll
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@@ -1,5 +1,5 @@
; RUN: llc < %s -march=cellspu -asm-verbose=0 > %t1.s ; RUN: llc < %s -march=cellspu -asm-verbose=0 -regalloc=linearscan > %t1.s
; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 > %t2.s ; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 -regalloc=linearscan > %t2.s
; RUN: grep bisl %t1.s | count 7 ; RUN: grep bisl %t1.s | count 7
; RUN: grep ila %t1.s | count 1 ; RUN: grep ila %t1.s | count 1
; RUN: grep rotqby %t1.s | count 5 ; RUN: grep rotqby %t1.s | count 5

6
test/CodeGen/CellSPU/jumptable.ll
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@@ -2,9 +2,9 @@
; This is to check that emitting jumptables doesn't crash llc ; This is to check that emitting jumptables doesn't crash llc
define i32 @test(i32 %param) { define i32 @test(i32 %param) {
entry: entry:
;CHECK: ai $4, $3, -1 ;CHECK: ai {{\$.}}, $3, -1
;CHECK: clgti $5, $4, 3 ;CHECK: clgti {{\$., \$.}}, 3
;CHECK: brnz $5,.LBB0_2 ;CHECK: brnz {{\$.}},.LBB0_2
switch i32 %param, label %bb1 [ switch i32 %param, label %bb1 [
i32 1, label %bb3 i32 1, label %bb3
i32 2, label %bb2 i32 2, label %bb2

16
test/CodeGen/CellSPU/loads.ll
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@@ -22,13 +22,15 @@ entry:
declare <4 x i32>* @getv4f32ptr() declare <4 x i32>* @getv4f32ptr()
define <4 x i32> @func() { define <4 x i32> @func() {
;CHECK: brasl ;CHECK: brasl
;CHECK: lr {{\$[0-9]*, \$3}} ; we need to have some instruction to move the result to safety.
;CHECK: brasl ; which instruction (lr, stqd...) depends on the regalloc
%rv1 = call <4 x i32>* @getv4f32ptr() ;CHECK: {{.*}}
%rv2 = call <4 x i32>* @getv4f32ptr() ;CHECK: brasl
%rv3 = load <4 x i32>* %rv1 %rv1 = call <4 x i32>* @getv4f32ptr()
ret <4 x i32> %rv3 %rv2 = call <4 x i32>* @getv4f32ptr()
%rv3 = load <4 x i32>* %rv1
ret <4 x i32> %rv3
} }
define <4 x float> @load_undef(){ define <4 x float> @load_undef(){