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Move LDM predicate operand encoding into base clase. Add STM missing STM

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encoding bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-11-10 23:44:32 +00:00
parent 5d5eb9e381
commit 954ffff79b
2 changed files with 18 additions and 10 deletions
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12
lib/Target/ARM/ARMInstrFormats.td
View File

@@ -940,9 +940,11 @@ class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
asm, cstr, pattern> { asm, cstr, pattern> {
bits<4> p;
bits<16> dsts; bits<16> dsts;
bits<4> Rn; bits<4> Rn;
bits<2> amode; bits<2> amode;
let Inst{31-28} = p;
let Inst{27-25} = 0b100; let Inst{27-25} = 0b100;
let Inst{24-23} = amode; let Inst{24-23} = amode;
let Inst{22} = 0; // S bit let Inst{22} = 0; // S bit
@@ -954,10 +956,16 @@ class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
asm, cstr, pattern> { asm, cstr, pattern> {
bits<4> p;
bits<16> srcs; bits<16> srcs;
let Inst{20} = 0; // L bit bits<4> Rn;
let Inst{22} = 0; // S bit bits<2> amode;
let Inst{31-28} = p;
let Inst{27-25} = 0b100; let Inst{27-25} = 0b100;
let Inst{24-23} = amode;
let Inst{22} = 0; // S bit
let Inst{20} = 0; // L bit
let Inst{19-16} = Rn;
let Inst{15-0} = srcs; let Inst{15-0} = srcs;
} }

16
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -1185,8 +1185,6 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
"ldm${mode}${p}\t$Rn!, $dsts", "ldm${mode}${p}\t$Rn!, $dsts",
"$Rn = $wb", []> { "$Rn = $wb", []> {
bits<4> p;
let Inst{31-28} = p;
let Inst{21} = 1; let Inst{21} = 1;
} }
@@ -1710,8 +1708,6 @@ def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iLoad_m, IndexModeNone, LdStMulFrm, IIC_iLoad_m,
"ldm${amode}${p}\t$Rn, $dsts", "", []> { "ldm${amode}${p}\t$Rn, $dsts", "", []> {
bits<4> p;
let Inst{31-28} = p;
let Inst{21} = 0; let Inst{21} = 0;
} }
@@ -1720,8 +1716,6 @@ def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
"ldm${amode}${p}\t$Rn!, $dsts", "ldm${amode}${p}\t$Rn!, $dsts",
"$Rn = $wb", []> { "$Rn = $wb", []> {
bits<4> p;
let Inst{31-28} = p;
let Inst{21} = 1; let Inst{21} = 1;
} }
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
@@ -1731,13 +1725,19 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iStore_m, IndexModeNone, LdStMulFrm, IIC_iStore_m,
"stm${amode}${p}\t$Rn, $srcs", "", []>; "stm${amode}${p}\t$Rn, $srcs", "", []> {
let Inst{21} = 0;
}
def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iStore_mu, IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
"stm${amode}${p}\t$Rn!, $srcs", "stm${amode}${p}\t$Rn!, $srcs",
"$Rn = $wb", []>; "$Rn = $wb", []> {
bits<4> p;
let Inst{31-28} = p;
let Inst{21} = 1;
}
} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//