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MC: Change RelaxInstruction to only take the input and output instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2010-05-26 18:15:06 +00:00
parent d9c2af5409
commit 95506d40c5
3 changed files with 13 additions and 12 deletions
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10
include/llvm/Target/TargetAsmBackend.h
View File

@ -16,7 +16,6 @@ namespace llvm {
class MCDataFragment;
class MCFixup;
class MCInst;
class MCInstFragment;
class MCObjectWriter;
class MCSection;
template<typename T>
@ -111,13 +110,16 @@ public:
/// MayNeedRelaxation - Check whether the given instruction may need
/// relaxation.
///
/// \arg Inst - The instruction to test.
/// \param Inst - The instruction to test.
virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0;
/// RelaxInstruction - Relax the instruction in the given fragment to the next
/// wider instruction.
virtual void RelaxInstruction(const MCInstFragment *IF,
MCInst &Res) const = 0;
///
/// \param Inst - The instruction to relax, which may be the same as the
/// output.
/// \parm Res [output] - On return, the relaxed instruction.
virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
/// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
/// output. If the target cannot generate such a sequence, it should return an

2
lib/MC/MCAssembler.cpp
View File

@ -824,7 +824,7 @@ bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) {
// Relax the fragment.
MCInst Relaxed;
getBackend().RelaxInstruction(IF, Relaxed);
getBackend().RelaxInstruction(IF->getInst(), Relaxed);
// Encode the new instruction.
//

13
lib/Target/X86/X86AsmBackend.cpp
View File

@ -56,7 +56,7 @@ public:
bool MayNeedRelaxation(const MCInst &Inst) const;
void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
};
@ -101,20 +101,19 @@ bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
// FIXME: Can tblgen help at all here to verify there aren't other instructions
// we can relax?
void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,
MCInst &Res) const {
void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
// The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode());
unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
if (RelaxedOp == IF->getInst().getOpcode()) {
if (RelaxedOp == Inst.getOpcode()) {
SmallString<256> Tmp;
raw_svector_ostream OS(Tmp);
IF->getInst().dump_pretty(OS);
Inst.dump_pretty(OS);
OS << "\n";
report_fatal_error("unexpected instruction to relax: " + OS.str());
}
Res = IF->getInst();
Res = Inst;
Res.setOpcode(RelaxedOp);
}