From 9568568b75f1c0b0042ac7cec6ad51ce8827d1e0 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 12 Aug 2002 21:25:05 +0000 Subject: [PATCH] - Clean up interface to Sparc register handling a bit: - Eliminate Sparc*Order classes, moving contents to Sparc*Class classes - get register name methods now return const char * const pointers instead of std::string's. - Added file header comments to SparcRegClassInfo.(cpp|h) - Moved BIG constant arrays out of SparcRegClassInfo.h, into SparcRegInfo.cpp. This should allow a LOT of std::string constructors to not have to be called. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3295 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SparcV9/SparcV9Internals.h | 2 +- .../SparcV9/SparcV9PrologEpilogInserter.cpp | 2 +- lib/Target/SparcV9/SparcV9RegClassInfo.cpp | 25 ++- lib/Target/SparcV9/SparcV9RegClassInfo.h | 186 ++++++------------ lib/Target/SparcV9/SparcV9RegInfo.cpp | 143 +++++++++----- 5 files changed, 171 insertions(+), 187 deletions(-) diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index 157004a104f..a3dc7c39742 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -419,7 +419,7 @@ public: // Returns the assembly-language name of the specified machine register. // - virtual const std::string getUnifiedRegName(int reg) const; + virtual const char * const getUnifiedRegName(int reg) const; // returns the # of bytes of stack space allocated for each register diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp index 179039ce8b8..a355f2ff634 100644 --- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp +++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp @@ -89,7 +89,7 @@ void InsertPrologEpilogCode::InsertPrologCode(Function &F) int32_t C = - (int) staticStackSize; int uregNum = Target.getRegInfo().getUnifiedRegNum( Target.getRegInfo().getRegClassIDOfType(Type::IntTy), - SparcIntRegOrder::l0); + SparcIntRegClass::l0); M = new MachineInstr(SETHI); M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed, C); diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp index 08e33245ba3..4d35f5d3e2b 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp @@ -1,8 +1,13 @@ +//===-- SparcRegClassInfo.cpp - Register class def'ns for Sparc -----------===// +// +// This file defines the register classes used by the Sparc target description. +// +//===----------------------------------------------------------------------===// + #include "SparcRegClassInfo.h" #include "llvm/CodeGen/RegAllocCommon.h" #include "llvm/Target/Sparc.h" #include "llvm/Type.h" -#include using std::cerr; using std::vector; @@ -61,17 +66,17 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) if( ! LR->isCallInterference() ) { // start with volatiles (we can allocate volatiles safely) - SearchStart = SparcIntRegOrder::StartOfAllRegs; + SearchStart = SparcIntRegClass::StartOfAllRegs; } else { // start with non volatiles (no non-volatiles) - SearchStart = SparcIntRegOrder::StartOfNonVolatileRegs; + SearchStart = SparcIntRegClass::StartOfNonVolatileRegs; } unsigned c=0; // color // find first unused color - for( c=SearchStart; c < SparcIntRegOrder::NumOfAvailRegs; c++) { + for( c=SearchStart; c < SparcIntRegClass::NumOfAvailRegs; c++) { if(!IsColorUsedArr[c] ) { ColorFound = true; break; } } @@ -86,10 +91,10 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) else if( LR->isCallInterference() ) { // start from 0 - try to find even a volatile this time - SearchStart = SparcIntRegOrder::StartOfAllRegs; + SearchStart = SparcIntRegClass::StartOfAllRegs; // find first unused volatile color - for(c=SearchStart; c < SparcIntRegOrder::StartOfNonVolatileRegs; c++) { + for(c=SearchStart; c < SparcIntRegClass::StartOfNonVolatileRegs; c++) { if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; } } @@ -200,11 +205,11 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node, //if this Node is between calls (i.e., no call interferences ) if( ! isCallInterf ) { // start with volatiles (we can allocate volatiles safely) - SearchStart = SparcFloatRegOrder::StartOfAllRegs; + SearchStart = SparcFloatRegClass::StartOfAllRegs; } else { // start with non volatiles (no non-volatiles) - SearchStart = SparcFloatRegOrder::StartOfNonVolatileRegs; + SearchStart = SparcFloatRegClass::StartOfNonVolatileRegs; } ColorFound = findFloatColor( LR, SearchStart, 32, IsColorUsedArr ); @@ -222,8 +227,8 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node, // color could be found. // Now try to allocate even a volatile color - ColorFound = findFloatColor( LR, SparcFloatRegOrder::StartOfAllRegs, - SparcFloatRegOrder::StartOfNonVolatileRegs, + ColorFound = findFloatColor( LR, SparcFloatRegClass::StartOfAllRegs, + SparcFloatRegClass::StartOfNonVolatileRegs, IsColorUsedArr); } diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.h b/lib/Target/SparcV9/SparcV9RegClassInfo.h index f07d0aa5f2b..467c3acf5f4 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.h +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.h @@ -1,12 +1,11 @@ -/* Title: SparcRegClassInfo.h -*- C++ -*- - Author: Ruchira Sasanka - Date: Aug 20, 01 - Purpose: Contains the description of integer register class of Sparc -*/ +//===-- SparcRegClassInfo.h - Register class def'ns for Sparc ----*- C++ -*--=// +// +// This file defines the register classes used by the Sparc target description. +// +//===----------------------------------------------------------------------===// - -#ifndef SPARC_REG_INFO_CLASS_H -#define SPARC_REG_INFO_CLASS_H +#ifndef SPARC_REG_CLASS_INFO_H +#define SPARC_REG_CLASS_INFO_H #include "llvm/Target/MachineRegInfo.h" #include "llvm/CodeGen/IGNode.h" @@ -15,21 +14,18 @@ // Integer Register Class //----------------------------------------------------------------------------- -// Int register names in same order as enum in class SparcIntRegOrder -static const std::string IntRegNames[] = { - "o0", "o1", "o2", "o3", "o4", "o5", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", - "i6", "i7", - "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o6" -}; +struct SparcIntRegClass : public MachineRegClassInfo { + SparcIntRegClass(unsigned ID) + : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { } + void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const; + inline bool isRegVolatile(int Reg) const { + return (Reg < (int)StartOfNonVolatileRegs); + } -struct SparcIntRegOrder { - enum RegsInPrefOrder { // colors possible for a LR (in preferred order) + enum { // colors possible for a LR (in preferred order) // --- following colors are volatile across function calls // %g0 can't be used for coloring - always 0 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5, @@ -49,7 +45,9 @@ struct SparcIntRegOrder { // --- following colors are not available for allocation within this phase // --- but can appear for pre-colored ranges - i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6 + i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6, + + NumOfAllRegs, // Must be first AFTER registers... //*** NOTE: If we decide to use some %g regs, they are volatile // (see sparc64ABI) @@ -57,36 +55,15 @@ struct SparcIntRegOrder { // enumeration of %o0 (change StartOfAllRegs below) // change isRegVloatile method below // Also change IntRegNames above. + + // max # of colors reg coloring can allocate + NumOfAvailRegs = i6, + + StartOfNonVolatileRegs = l0, + StartOfAllRegs = o0, }; - // max # of colors reg coloring can allocate - static unsigned int const NumOfAvailRegs = i6; - - static unsigned int const StartOfNonVolatileRegs = l0; - static unsigned int const StartOfAllRegs = o0; - static unsigned int const NumOfAllRegs = o6 + 1; - - - static const std::string getRegName(unsigned reg) { - assert( reg < NumOfAllRegs ); - return IntRegNames[reg]; - } - -}; - - - -struct SparcIntRegClass : public MachineRegClassInfo { - SparcIntRegClass(unsigned ID) - : MachineRegClassInfo(ID, - SparcIntRegOrder::NumOfAvailRegs, - SparcIntRegOrder::NumOfAllRegs) { } - - void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const; - - inline bool isRegVolatile(int Reg) const { - return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs); - } + static const char * const getRegName(unsigned reg); }; @@ -96,65 +73,38 @@ struct SparcIntRegClass : public MachineRegClassInfo { // Float Register Class //----------------------------------------------------------------------------- -static const std::string FloatRegNames[] = - { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", - "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", - "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", - "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", - "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", - "f60", "f61", "f62", "f63" - }; +class SparcFloatRegClass : public MachineRegClassInfo { + int findFloatColor(const LiveRange *LR, unsigned Start, + unsigned End, std::vector &IsColorUsedArr) const; +public: + SparcFloatRegClass(unsigned ID) + : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {} + void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const; -class SparcFloatRegOrder{ - - public: - - enum RegsInPrefOrder { + // according to Sparc 64 ABI, all %fp regs are volatile + inline bool isRegVolatile(int Reg) const { return true; } + enum { f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, f31, f32, f33, f34, f35, f36, f37, f38, f39, f40, f41, f42, f43, f44, f45, f46, f47, f48, f49, f50, f51, f52, f53, f54, f55, f56, f57, f58, f59, - f60, f61, f62, f63 + f60, f61, f62, f63, + // there are 64 regs alltogether but only 32 regs can be allocated at + // a time. + // + NumOfAvailRegs = 32, + NumOfAllRegs = 64, + + StartOfNonVolatileRegs = f32, + StartOfAllRegs = f0, }; - // there are 64 regs alltogether but only 32 regs can be allocated at - // a time. - - static unsigned int const NumOfAvailRegs = 32; - static unsigned int const NumOfAllRegs = 64; - - static unsigned int const StartOfNonVolatileRegs = f32; - static unsigned int const StartOfAllRegs = f0; - - - static const std::string getRegName(unsigned reg) { - assert (reg < NumOfAllRegs); - return FloatRegNames[reg]; - } -}; - - - -class SparcFloatRegClass : public MachineRegClassInfo { - int findFloatColor(const LiveRange *LR, unsigned Start, - unsigned End, std::vector &IsColorUsedArr) const; -public: - SparcFloatRegClass(unsigned ID) - : MachineRegClassInfo(ID, - SparcFloatRegOrder::NumOfAvailRegs, - SparcFloatRegOrder::NumOfAllRegs) {} - - void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const; - - // according to Sparc 64 ABI, all %fp regs are volatile - inline bool isRegVolatile(int Reg) const { return true; } + static const char * const getRegName(unsigned reg); }; @@ -169,25 +119,6 @@ public: // allocated for two names. //----------------------------------------------------------------------------- - -static const std::string IntCCRegNames[] = { - "xcc", "ccr" -}; - - -struct SparcIntCCRegOrder { - enum RegsInPrefOrder { - xcc, ccr // only one is available - see the note above - }; - - static const std::string getRegName(unsigned reg) { - assert(reg < 2); - return IntCCRegNames[reg]; - } -}; - - - struct SparcIntCCRegClass : public MachineRegClassInfo { SparcIntCCRegClass(unsigned ID) : MachineRegClassInfo(ID, 1, 2) { } @@ -202,6 +133,12 @@ struct SparcIntCCRegClass : public MachineRegClassInfo { // according to Sparc 64 ABI, %ccr is volatile // inline bool isRegVolatile(int Reg) const { return true; } + + enum { + xcc, ccr // only one is available - see the note above + }; + + static const char * const getRegName(unsigned reg); }; @@ -212,21 +149,6 @@ struct SparcIntCCRegClass : public MachineRegClassInfo { // Only 4 Float CC registers are available //----------------------------------------------------------------------------- -static const std::string FloatCCRegNames[] = { - "fcc0", "fcc1", "fcc2", "fcc3" -}; - -struct SparcFloatCCRegOrder{ - enum RegsInPrefOrder { - fcc0, fcc1, fcc2, fcc3 - }; - - static const std::string getRegName(unsigned reg) { - assert (reg < 4); - return FloatCCRegNames[reg]; - } -}; - struct SparcFloatCCRegClass : public MachineRegClassInfo { SparcFloatCCRegClass(unsigned ID) : MachineRegClassInfo(ID, 4, 4) { } @@ -244,6 +166,12 @@ struct SparcFloatCCRegClass : public MachineRegClassInfo { // according to Sparc 64 ABI, all %fp CC regs are volatile // inline bool isRegVolatile(int Reg) const { return true; } + + enum { + fcc0, fcc1, fcc2, fcc3 + }; + + static const char * const getRegName(unsigned reg); }; #endif diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index b875dbed224..4625773a133 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -34,7 +34,7 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID)); MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID)); - assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 && + assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 && "32 Float regs are used for float arg passing"); } @@ -43,16 +43,16 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) // this is the unified register number // int UltraSparcRegInfo::getZeroRegNum() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::g0); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::g0); } // getCallAddressReg - returns the reg used for pushing the address when a // method is called. This can be used for other purposes between calls // unsigned UltraSparcRegInfo::getCallAddressReg() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::o7); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::o7); } // Returns the register containing the return address. @@ -60,22 +60,73 @@ unsigned UltraSparcRegInfo::getCallAddressReg() const { // value when a return instruction is reached. // unsigned UltraSparcRegInfo::getReturnAddressReg() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::i7); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::i7); +} + +// Register get name implementations... + +// Int register names in same order as enum in class SparcIntRegClass +static const char * const IntRegNames[] = { + "o0", "o1", "o2", "o3", "o4", "o5", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", + "i6", "i7", + "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o6" +}; + +const char * const SparcIntRegClass::getRegName(unsigned reg) { + assert(reg < NumOfAllRegs); + return IntRegNames[reg]; +} + +static const char * const FloatRegNames[] = { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", + "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", + "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", + "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", + "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", + "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", + "f60", "f61", "f62", "f63" +}; + +const char * const SparcFloatRegClass::getRegName(unsigned reg) { + assert (reg < NumOfAllRegs); + return FloatRegNames[reg]; +} + + +static const char * const IntCCRegNames[] = { + "xcc", "ccr" +}; + +const char * const SparcIntCCRegClass::getRegName(unsigned reg) { + assert(reg < 2); + return IntCCRegNames[reg]; +} + +static const char * const FloatCCRegNames[] = { + "fcc0", "fcc1", "fcc2", "fcc3" +}; + +const char * const SparcFloatCCRegClass::getRegName(unsigned reg) { + assert (reg < 4); + return FloatCCRegNames[reg]; } // given the unified register number, this gives the name // for generating assembly code or debugging. // -const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const { +const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const { if( reg < 32 ) - return SparcIntRegOrder::getRegName(reg); + return SparcIntRegClass::getRegName(reg); else if ( reg < (64 + 32) ) - return SparcFloatRegOrder::getRegName( reg - 32); + return SparcFloatRegClass::getRegName( reg - 32); else if( reg < (64+32+4) ) - return SparcFloatCCRegOrder::getRegName( reg -32 - 64); + return SparcFloatCCRegClass::getRegName( reg -32 - 64); else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr - return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4); + return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4); else if (reg== InvalidRegNum) //****** TODO: Remove */ return "<*NoReg*>"; else @@ -85,14 +136,14 @@ const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const { // Get unified reg number for frame pointer unsigned UltraSparcRegInfo::getFramePointer() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::i6); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::i6); } // Get unified reg number for stack pointer unsigned UltraSparcRegInfo::getStackPointer() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::o6); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::o6); } @@ -135,7 +186,7 @@ UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall, if (argNo >= NumOfIntArgRegs) return InvalidRegNum; else - return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0); + return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0); } // Get the register number for the specified FP arg#, @@ -162,10 +213,10 @@ UltraSparcRegInfo::regNumForFPArg(unsigned regType, regClassId = FloatRegClassID; if (regType == FPSingleRegType) return (argNo*2+1 >= NumOfFloatArgRegs)? - InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1); + InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2 + 1); else if (regType == FPDoubleRegType) return (argNo*2 >= NumOfFloatArgRegs)? - InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2); + InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2); else assert(0 && "Illegal FP register type"); return 0; @@ -279,7 +330,7 @@ void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI, // return address is always mapped to i7 so set it immediately RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID, - SparcIntRegOrder::i7)); + SparcIntRegClass::i7)); // Possible Optimization: // Instead of setting the color, we can suggest one. In that case, @@ -312,7 +363,7 @@ void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI, RetAddrLR->insert( RetAddrVal ); unsigned RegClassID = getRegClassIDOfValue( RetAddrVal ); RetAddrLR->setRegClass( RCList[RegClassID] ); - RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7)); + RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegClass::o7)); LRI.addLRToMap( RetAddrVal, RetAddrLR); } @@ -548,9 +599,9 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, // now suggest a register depending on the register class of ret arg if( RegClassID == IntRegClassID ) - RetValLR->setSuggestedColor(SparcIntRegOrder::o0); + RetValLR->setSuggestedColor(SparcIntRegClass::o0); else if (RegClassID == FloatRegClassID ) - RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 ); + RetValLR->setSuggestedColor(SparcFloatRegClass::f0 ); else assert( 0 && "Unknown reg class for return value of call\n"); } @@ -748,16 +799,16 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, unsigned UniRetReg; // unified number for CorrectCol if(RegClassID == IntRegClassID) - CorrectCol = SparcIntRegOrder::o0; + CorrectCol = SparcIntRegClass::o0; else if(RegClassID == FloatRegClassID) - CorrectCol = SparcFloatRegOrder::f0; + CorrectCol = SparcFloatRegClass::f0; else { assert( 0 && "Unknown RegClass"); return; } // convert to unified number - UniRetReg = this->getUnifiedRegNum( RegClassID, CorrectCol); + UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol); // Mark the register as used by this instruction CallMI->getRegsUsed().insert(UniRetReg); @@ -947,9 +998,9 @@ void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, unsigned RegClassID = (LR->getRegClass())->getID(); if (RegClassID == IntRegClassID) - LR->setSuggestedColor(SparcIntRegOrder::i0); + LR->setSuggestedColor(SparcIntRegClass::i0); else if (RegClassID == FloatRegClassID) - LR->setSuggestedColor(SparcFloatRegOrder::f0); + LR->setSuggestedColor(SparcFloatRegClass::f0); } } @@ -986,16 +1037,16 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, unsigned CorrectCol; if(RegClassID == IntRegClassID) - CorrectCol = SparcIntRegOrder::i0; + CorrectCol = SparcIntRegClass::i0; else if(RegClassID == FloatRegClassID) - CorrectCol = SparcFloatRegOrder::f0; + CorrectCol = SparcFloatRegClass::f0; else { assert (0 && "Unknown RegClass"); return; } // convert to unified number - unsigned UniRetReg = this->getUnifiedRegNum(RegClassID, CorrectCol); + unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol); // Mark the register as used by this instruction RetMI->getRegsUsed().insert(UniRetReg); @@ -1067,7 +1118,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, switch( RegType ) { case IntCCRegType: - if (this->getRegType(DestReg) == IntRegType) + if (getRegType(DestReg) == IntRegType) { // copy intCC reg to int reg // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg); @@ -1075,7 +1126,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, else { // copy int reg to intCC reg // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR - assert(this->getRegType(SrcReg) == IntRegType + assert(getRegType(SrcReg) == IntRegType && "Can only copy CC reg to/from integer reg"); MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1); } @@ -1086,7 +1137,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, break; case IntRegType: - MI = Create3OperandInstr_Reg(ADD, SrcReg, this->getZeroRegNum(), DestReg); + MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg); break; case FPSingleRegType: @@ -1149,13 +1200,13 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, case IntCCRegType: assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory"); - assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); + assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg); mvec.push_back(MI); - this->cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType); + cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType); break; case FloatCCRegType: @@ -1218,8 +1269,8 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, case IntCCRegType: assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory"); - assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); - this->cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType); + assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); + cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType); // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1); @@ -1263,7 +1314,7 @@ UltraSparcRegInfo::cpValue2Value(Value *Src, case IntRegType: MI = new MachineInstr(ADD, 3); MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandReg(1, this->getZeroRegNum(), false); + MI->SetMachineOperandReg(1, getZeroRegNum(), false); MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true); break; @@ -1390,13 +1441,13 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, // the save code. int scratchRegType = -1; int scratchReg = -1; - if (this->regTypeNeedsScratchReg(RegType, scratchRegType)) + if (regTypeNeedsScratchReg(RegType, scratchRegType)) { // Find a register not live in the LVSet before CallMI const ValueSet &LVSetBef = PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB); scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef, CallMI, AdIBef, AdIAft); - assert(scratchReg != this->getInvalidRegNum()); + assert(scratchReg != getInvalidRegNum()); CallMI->getRegsUsed().insert(scratchReg); } @@ -1420,11 +1471,11 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, // scratchRegType = -1; scratchReg = -1; - if (this->regTypeNeedsScratchReg(RegType, scratchRegType)) + if (regTypeNeedsScratchReg(RegType, scratchRegType)) { // Find a register not live in the LVSet after CallMI scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft, CallMI, AdIBef, AdIAft); - assert(scratchReg != this->getInvalidRegNum()); + assert(scratchReg != getInvalidRegNum()); CallMI->getRegsUsed().insert(scratchReg); } @@ -1480,12 +1531,12 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) { cerr << " colored with color "<< LR->getColor(); if (RegClassID == IntRegClassID) { - cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n"; + cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n"; } else if (RegClassID == FloatRegClassID) { - cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor()); + cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor()); if( LR->getType() == Type::DoubleTy) - cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1); + cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1); cerr << "]\n"; } }