mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
9c0a05c7af
commit
958cc01fff
@ -1388,6 +1388,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw256">,
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Intrinsic<[llvm_v4i64_ty], [llvm_v32i8_ty,
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llvm_v32i8_ty], [IntrNoMem, Commutative]>;
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def int_x86_avx512_mask_pmulu_dq_512 : GCCBuiltin<"__builtin_ia32_pmuludq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pmul_dq_512 : GCCBuiltin<"__builtin_ia32_pmuldq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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}
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// Vector min, max
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@ -1428,6 +1434,30 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_pmins_d : GCCBuiltin<"__builtin_ia32_pminsd256">,
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Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
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llvm_v8i32_ty], [IntrNoMem, Commutative]>;
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def int_x86_avx512_mask_pmaxu_d_512 : GCCBuiltin<"__builtin_ia32_pmaxud512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pmaxs_d_512 : GCCBuiltin<"__builtin_ia32_pmaxsd512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pmaxu_q_512 : GCCBuiltin<"__builtin_ia32_pmaxuq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
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llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pmaxs_q_512 : GCCBuiltin<"__builtin_ia32_pmaxsq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
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llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pminu_d_512 : GCCBuiltin<"__builtin_ia32_pminud512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pmins_d_512 : GCCBuiltin<"__builtin_ia32_pminsd512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pminu_q_512 : GCCBuiltin<"__builtin_ia32_pminuq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
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llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pmins_q_512 : GCCBuiltin<"__builtin_ia32_pminsq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
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llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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}
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// Integer shift ops.
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@ -1520,6 +1550,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty], [IntrNoMem]>;
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def int_x86_avx2_pabs_d : GCCBuiltin<"__builtin_ia32_pabsd256">,
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Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pabs_d_512 : GCCBuiltin<"__builtin_ia32_pabsd512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_pabs_q_512 : GCCBuiltin<"__builtin_ia32_pabsq512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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}
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// Horizontal arithmetic ops
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@ -2822,32 +2858,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
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llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_pmaxu_d : GCCBuiltin<"__builtin_ia32_pmaxud512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
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llvm_v16i32_ty], [IntrNoMem]>;
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def int_x86_avx512_pmaxu_q : GCCBuiltin<"__builtin_ia32_pmaxuq512">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
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llvm_v8i64_ty], [IntrNoMem]>;
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def int_x86_avx512_pmaxs_d : GCCBuiltin<"__builtin_ia32_pmaxsd512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
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llvm_v16i32_ty], [IntrNoMem]>;
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def int_x86_avx512_pmaxs_q : GCCBuiltin<"__builtin_ia32_pmaxsq512">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
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llvm_v8i64_ty], [IntrNoMem]>;
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def int_x86_avx512_pminu_d : GCCBuiltin<"__builtin_ia32_pminud512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
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llvm_v16i32_ty], [IntrNoMem]>;
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def int_x86_avx512_pminu_q : GCCBuiltin<"__builtin_ia32_pminuq512">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
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llvm_v8i64_ty], [IntrNoMem]>;
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def int_x86_avx512_pmins_d : GCCBuiltin<"__builtin_ia32_pminsd512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
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llvm_v16i32_ty], [IntrNoMem]>;
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def int_x86_avx512_pmins_q : GCCBuiltin<"__builtin_ia32_pminsq512">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
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llvm_v8i64_ty], [IntrNoMem]>;
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def int_x86_avx512_rndscale_ss : GCCBuiltin<"__builtin_ia32_rndscaless">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_i32_ty], [IntrNoMem]>;
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@ -3088,22 +3098,22 @@ let TargetPrefix = "x86" in {
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// Vector blend
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_mask_blend_ps_512 : GCCBuiltin<"__builtin_ia32_mask_blendps512">,
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def int_x86_avx512_mask_blend_ps_512 : GCCBuiltin<"__builtin_ia32_blendmps_512_mask">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v16i1_ty, llvm_v16f32_ty, llvm_v16f32_ty],
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[llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_blend_pd_512 : GCCBuiltin<"__builtin_ia32_mask_blendpd512">,
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def int_x86_avx512_mask_blend_pd_512 : GCCBuiltin<"__builtin_ia32_blendmpd_512_mask">,
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Intrinsic<[llvm_v8f64_ty],
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[llvm_v8i1_ty, llvm_v8f64_ty, llvm_v8f64_ty],
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[llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_blend_d_512 : GCCBuiltin<"__builtin_ia32_mask_blendd512">,
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def int_x86_avx512_mask_blend_d_512 : GCCBuiltin<"__builtin_ia32_blendmd_512_mask">,
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Intrinsic<[llvm_v16i32_ty],
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[llvm_v16i1_ty, llvm_v16i32_ty, llvm_v16i32_ty],
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[llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_blend_q_512 : GCCBuiltin<"__builtin_ia32_mask_blendq512">,
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def int_x86_avx512_mask_blend_q_512 : GCCBuiltin<"__builtin_ia32_blendmq_512_mask">,
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v8i1_ty, llvm_v8i64_ty, llvm_v8i64_ty],
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[llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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}
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@ -11383,32 +11383,24 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_avx2_pmaxu_b:
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case Intrinsic::x86_avx2_pmaxu_w:
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case Intrinsic::x86_avx2_pmaxu_d:
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case Intrinsic::x86_avx512_pmaxu_d:
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case Intrinsic::x86_avx512_pmaxu_q:
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case Intrinsic::x86_sse2_pminu_b:
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case Intrinsic::x86_sse41_pminuw:
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case Intrinsic::x86_sse41_pminud:
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case Intrinsic::x86_avx2_pminu_b:
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case Intrinsic::x86_avx2_pminu_w:
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case Intrinsic::x86_avx2_pminu_d:
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case Intrinsic::x86_avx512_pminu_d:
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case Intrinsic::x86_avx512_pminu_q:
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case Intrinsic::x86_sse41_pmaxsb:
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case Intrinsic::x86_sse2_pmaxs_w:
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case Intrinsic::x86_sse41_pmaxsd:
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case Intrinsic::x86_avx2_pmaxs_b:
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case Intrinsic::x86_avx2_pmaxs_w:
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case Intrinsic::x86_avx2_pmaxs_d:
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case Intrinsic::x86_avx512_pmaxs_d:
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case Intrinsic::x86_avx512_pmaxs_q:
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case Intrinsic::x86_sse41_pminsb:
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case Intrinsic::x86_sse2_pmins_w:
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case Intrinsic::x86_sse41_pminsd:
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case Intrinsic::x86_avx2_pmins_b:
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case Intrinsic::x86_avx2_pmins_w:
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case Intrinsic::x86_avx2_pmins_d:
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case Intrinsic::x86_avx512_pmins_d:
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case Intrinsic::x86_avx512_pmins_q: {
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case Intrinsic::x86_avx2_pmins_d: {
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unsigned Opcode;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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@ -11418,8 +11410,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_avx2_pmaxu_b:
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case Intrinsic::x86_avx2_pmaxu_w:
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case Intrinsic::x86_avx2_pmaxu_d:
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case Intrinsic::x86_avx512_pmaxu_d:
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case Intrinsic::x86_avx512_pmaxu_q:
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Opcode = X86ISD::UMAX;
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break;
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case Intrinsic::x86_sse2_pminu_b:
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@ -11428,8 +11418,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_avx2_pminu_b:
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case Intrinsic::x86_avx2_pminu_w:
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case Intrinsic::x86_avx2_pminu_d:
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case Intrinsic::x86_avx512_pminu_d:
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case Intrinsic::x86_avx512_pminu_q:
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Opcode = X86ISD::UMIN;
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break;
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case Intrinsic::x86_sse41_pmaxsb:
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@ -11438,8 +11426,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_avx2_pmaxs_b:
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case Intrinsic::x86_avx2_pmaxs_w:
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case Intrinsic::x86_avx2_pmaxs_d:
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case Intrinsic::x86_avx512_pmaxs_d:
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case Intrinsic::x86_avx512_pmaxs_q:
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Opcode = X86ISD::SMAX;
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break;
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case Intrinsic::x86_sse41_pminsb:
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@ -11448,8 +11434,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_avx2_pmins_b:
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case Intrinsic::x86_avx2_pmins_w:
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case Intrinsic::x86_avx2_pmins_d:
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case Intrinsic::x86_avx512_pmins_d:
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case Intrinsic::x86_avx512_pmins_q:
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Opcode = X86ISD::SMIN;
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break;
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}
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@ -608,68 +608,65 @@ defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem
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//===----------------------------------------------------------------------===//
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// AVX-512 - BLEND using mask
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//
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multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
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multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
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RegisterClass KRC, RegisterClass RC,
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X86MemOperand x86memop, PatFrag mem_frag,
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SDNode OpNode, ValueType vt> {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
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(ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
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(vt RC:$src1)))]>, EVEX_4V, EVEX_K;
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let isCodeGenOnly = 1 in
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def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
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(vt RC:$src1)))]>, EVEX_4V, EVEX_K;
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let mayLoad = 1 in {
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[]>,
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EVEX_4V, EVEX_K;
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let isCodeGenOnly = 1 in
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def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
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(mem_frag addr:$src2)))]>,
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EVEX_4V, EVEX_K;
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}
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let mayLoad = 1 in
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[]>, EVEX_4V, EVEX_K;
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}
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let ExeDomain = SSEPackedSingle in
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defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
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int_x86_avx512_mask_blend_ps_512,
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VK16WM, VR512, f512mem,
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memopv16f32, vselect, v16f32>,
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EVEX_CD8<32, CD8VF>, EVEX_V512;
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let ExeDomain = SSEPackedDouble in
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defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
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int_x86_avx512_mask_blend_pd_512,
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VK8WM, VR512, f512mem,
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memopv8f64, vselect, v8f64>,
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VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
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def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
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(v16f32 VR512:$src2), (i16 GR16:$mask))),
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(VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
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VR512:$src1, VR512:$src2)>;
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def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
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(v8f64 VR512:$src2), (i8 GR8:$mask))),
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(VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
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VR512:$src1, VR512:$src2)>;
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defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
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int_x86_avx512_mask_blend_d_512,
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VK16WM, VR512, f512mem,
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memopv16i32, vselect, v16i32>,
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EVEX_CD8<32, CD8VF>, EVEX_V512;
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defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
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int_x86_avx512_mask_blend_q_512,
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VK8WM, VR512, f512mem,
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memopv8i64, vselect, v8i64>,
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VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
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def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (i16 GR16:$mask))),
|
||||
(VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
|
||||
VR512:$src1, VR512:$src2)>;
|
||||
|
||||
def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2), (i8 GR8:$mask))),
|
||||
(VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
|
||||
VR512:$src1, VR512:$src2)>;
|
||||
|
||||
let Predicates = [HasAVX512] in {
|
||||
def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
|
||||
(v8f32 VR256X:$src2))),
|
||||
@ -1780,6 +1777,13 @@ defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
|
||||
def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
|
||||
(VPMULUDQZrr VR512:$src1, VR512:$src2)>;
|
||||
|
||||
def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPMULUDQZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPMULDQZrr VR512:$src1, VR512:$src2)>;
|
||||
|
||||
defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
|
||||
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
|
||||
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
@ -1789,7 +1793,7 @@ defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i
|
||||
|
||||
defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
|
||||
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
|
||||
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
|
||||
T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
@ -1808,6 +1812,30 @@ defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i
|
||||
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
|
||||
T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
|
||||
(VPMAXSDZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
|
||||
(VPMAXUDZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPMAXSQZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPMAXUQZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
|
||||
(VPMINSDZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
|
||||
(VPMINUDZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPMINSQZrr VR512:$src1, VR512:$src2)>;
|
||||
def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPMINUQZrr VR512:$src1, VR512:$src2)>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AVX-512 - Unpack Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -3773,6 +3801,13 @@ defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
|
||||
defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
|
||||
(v16i32 immAllZerosV), (i16 -1))),
|
||||
(VPABSDrr VR512:$src)>;
|
||||
def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
|
||||
(bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VPABSQrr VR512:$src)>;
|
||||
|
||||
multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
|
||||
RegisterClass RC, RegisterClass KRC,
|
||||
X86MemOperand x86memop,
|
||||
|
||||
@ -1420,6 +1420,10 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
{ X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
|
||||
{ X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
|
||||
{ X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
|
||||
{ X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
|
||||
{ X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
|
||||
{ X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
|
||||
{ X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }
|
||||
};
|
||||
|
||||
for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
|
||||
|
||||
@ -290,62 +290,6 @@ define <8 x i64> @test_x86_pbroadcastq_i64_512(i64 %a0) {
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.pbroadcastq.i64.512(i64) nounwind readonly
|
||||
|
||||
define <16 x i32> @test_x86_pmaxu_d(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpmaxud
|
||||
%res = call <16 x i32> @llvm.x86.avx512.pmaxu.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.pmaxu.d(<16 x i32>, <16 x i32>) nounwind readonly
|
||||
|
||||
define <8 x i64> @test_x86_pmaxu_q(<8 x i64> %a0, <8 x i64> %a1) {
|
||||
; CHECK: vpmaxuq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.pmaxu.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.pmaxu.q(<8 x i64>, <8 x i64>) nounwind readonly
|
||||
|
||||
define <16 x i32> @test_x86_pmaxs_d(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpmaxsd
|
||||
%res = call <16 x i32> @llvm.x86.avx512.pmaxs.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.pmaxs.d(<16 x i32>, <16 x i32>) nounwind readonly
|
||||
|
||||
define <8 x i64> @test_x86_pmaxs_q(<8 x i64> %a0, <8 x i64> %a1) {
|
||||
; CHECK: vpmaxsq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.pmaxs.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.pmaxs.q(<8 x i64>, <8 x i64>) nounwind readonly
|
||||
|
||||
define <16 x i32> @test_x86_pminu_d(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpminud
|
||||
%res = call <16 x i32> @llvm.x86.avx512.pminu.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.pminu.d(<16 x i32>, <16 x i32>) nounwind readonly
|
||||
|
||||
define <8 x i64> @test_x86_pminu_q(<8 x i64> %a0, <8 x i64> %a1) {
|
||||
; CHECK: vpminuq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.pminu.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.pminu.q(<8 x i64>, <8 x i64>) nounwind readonly
|
||||
|
||||
define <16 x i32> @test_x86_pmins_d(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpminsd
|
||||
%res = call <16 x i32> @llvm.x86.avx512.pmins.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.pmins.d(<16 x i32>, <16 x i32>) nounwind readonly
|
||||
|
||||
define <8 x i64> @test_x86_pmins_q(<8 x i64> %a0, <8 x i64> %a1) {
|
||||
; CHECK: vpminsq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.pmins.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.pmins.q(<8 x i64>, <8 x i64>) nounwind readonly
|
||||
|
||||
define <16 x i32> @test_conflict_d(<16 x i32> %a) {
|
||||
; CHECK: movw $-1, %ax
|
||||
; CHECK: vpxor
|
||||
@ -381,45 +325,40 @@ define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
|
||||
|
||||
define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
|
||||
; CHECK: vblendmps
|
||||
%m0 = bitcast i16 %a0 to <16 x i1>
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x i1> %m0, <16 x float> %a1, <16 x float> %a2) ; <<16 x float>> [#uses=1]
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float> %a1, <16 x float> %a2, i16 %a0) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
}
|
||||
|
||||
declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x i1> %a0, <16 x float> %a1, <16 x float> %a2) nounwind readonly
|
||||
declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float>, <16 x float>, i16) nounwind readonly
|
||||
|
||||
define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x double> %a2) {
|
||||
; CHECK: vblendmpd
|
||||
%m0 = bitcast i8 %a0 to <8 x i1>
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x i1> %m0, <8 x double> %a1, <8 x double> %a2) ; <<8 x double>> [#uses=1]
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a1, <8 x double> %a2, i8 %a0) ; <<8 x double>> [#uses=1]
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
define <8 x double> @test_x86_mask_blend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) {
|
||||
; CHECK-LABEL: test_x86_mask_blend_pd_512_memop
|
||||
; CHECK: vblendmpd {{.*}}, {{%zmm[0-9]}}, {{%zmm[0-9]}} {%k1}
|
||||
%vmask = bitcast i8 %mask to <8 x i1>
|
||||
; CHECK: vblendmpd (%
|
||||
%b = load <8 x double>* %ptr
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x i1> %vmask, <8 x double> %a, <8 x double> %b) ; <<8 x double>> [#uses=1]
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a, <8 x double> %b, i8 %mask) ; <<8 x double>> [#uses=1]
|
||||
ret <8 x double> %res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x i1> %a0, <8 x double> %a1, <8 x double> %a2) nounwind readonly
|
||||
declare <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double>, <8 x double>, i8) nounwind readonly
|
||||
|
||||
define <16 x i32> @test_x86_mask_blend_d_512(i16 %a0, <16 x i32> %a1, <16 x i32> %a2) {
|
||||
; CHECK: vpblendmd
|
||||
%m0 = bitcast i16 %a0 to <16 x i1>
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i1> %m0, <16 x i32> %a1, <16 x i32> %a2) ; <<16 x i32>> [#uses=1]
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32> %a1, <16 x i32> %a2, i16 %a0) ; <<16 x i32>> [#uses=1]
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i1> %a0, <16 x i32> %a1, <16 x i32> %a2) nounwind readonly
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
|
||||
|
||||
define <8 x i64> @test_x86_mask_blend_q_512(i8 %a0, <8 x i64> %a1, <8 x i64> %a2) {
|
||||
; CHECK: vpblendmq
|
||||
%m0 = bitcast i8 %a0 to <8 x i1>
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i1> %m0, <8 x i64> %a1, <8 x i64> %a2) ; <<8 x i64>> [#uses=1]
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64> %a1, <8 x i64> %a2, i8 %a0) ; <<8 x i64>> [#uses=1]
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i1> %a0, <8 x i64> %a1, <8 x i64> %a2) nounwind readonly
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
|
||||
|
||||
define <8 x i32> @test_cvtpd2udq(<8 x double> %a) {
|
||||
;CHECK: vcvtpd2udq {ru-sae}{{.*}}encoding: [0x62,0xf1,0xfc,0x58,0x79,0xc0]
|
||||
@ -521,3 +460,49 @@ declare <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double>, <8 x double>
|
||||
ret <8 x float>%res
|
||||
}
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)
|
||||
|
||||
define <16 x i32> @test_pabsd(<16 x i32> %a) {
|
||||
;CHECK: vpabsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x1e,0xc0]
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %a, <16 x i32>zeroinitializer, i16 -1)
|
||||
ret < 16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32>, <16 x i32>, i16)
|
||||
|
||||
define <8 x i64> @test_pabsq(<8 x i64> %a) {
|
||||
;CHECK: vpabsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x1f,0xc0]
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %a, <8 x i64>zeroinitializer, i8 -1)
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8)
|
||||
|
||||
define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {
|
||||
; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,
|
||||
<8 x i64>zeroinitializer, i8 -1)
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
|
||||
|
||||
define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %a0, <16 x i32> %a1,
|
||||
<16 x i32>zeroinitializer, i16 -1)
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
|
||||
|
||||
define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %a0, <16 x i32> %a1,
|
||||
<16 x i32>zeroinitializer, i16 -1)
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
|
||||
|
||||
define <8 x i64> @test_vpmuludq(<16 x i32> %a0, <16 x i32> %a1) {
|
||||
; CHECK: vpmuludq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xf4,0xc1]
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a0, <16 x i32> %a1,
|
||||
<8 x i64>zeroinitializer, i8 -1)
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user