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R600/SI: Really fix size of VReg_1

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2015-02-14 03:54:32 +00:00
parent b79a67d967
commit 958cf585ce
1 changed files with 3 additions and 1 deletions
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4
lib/Target/R600/SIRegisterInfo.td
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@ -209,7 +209,9 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
let Size = 32;
}
class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
let OperandNamespace = "AMDGPU";