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Preparation for adding simple Mips64 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-09-24 01:34:44 +00:00
parent 51f0c76419
commit 95934844e3
3 changed files with 8 additions and 0 deletions
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2
.gitignore vendored
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@ -17,11 +17,13 @@
*.pyc
# vim swap files
.*.swp
*.patch
#==============================================================================#
# Explicit files to ignore (only matches one).
#==============================================================================#
.gitusers
.svn
autom4te.cache
cscope.files
cscope.out

5
lib/Target/Mips/MipsISelLowering.cpp
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@ -95,6 +95,9 @@ MipsTargetLowering(MipsTargetMachine &TM)
addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
if (HasMips64)
addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) {
if (HasMips64)
@ -2260,6 +2263,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
if (RegVT == MVT::i32)
RC = Mips::CPURegsRegisterClass;
else if (RegVT == MVT::i64)
RC = Mips::CPU64RegsRegisterClass;
else if (RegVT == MVT::f32)
RC = Mips::FGR32RegisterClass;
else if (RegVT == MVT::f64) {

1
lib/Target/Mips/MipsInstrInfo.td
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@ -879,4 +879,5 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
//===----------------------------------------------------------------------===//
include "MipsInstrFPU.td"
include "Mips64InstrInfo.td"