mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
This patch continues the work of adding instruction latencies for X86 Atom,
by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Preston Gurd
parent
e2849851b2
commit
95f0cf0438
@ -423,24 +423,40 @@ def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
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}
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let mayLoad = 1 in {
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
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def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
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def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
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def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
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def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
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def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src",
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IIC_FLD>;
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def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src",
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IIC_FLD>;
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def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src",
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IIC_FLD80>;
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def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src",
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IIC_FILD>;
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def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src",
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IIC_FILD>;
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def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src",
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IIC_FILD>;
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}
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let mayStore = 1 in {
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def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
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def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
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def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
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def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
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def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
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def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
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def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
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def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
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def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
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def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
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def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst",
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IIC_FST>;
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def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst",
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IIC_FST>;
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def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst",
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IIC_FST>;
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def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst",
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IIC_FST>;
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def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst",
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IIC_FST80>;
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def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst",
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IIC_FIST>;
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def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst",
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IIC_FIST>;
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def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst",
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IIC_FIST>;
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def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst",
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IIC_FIST>;
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def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst",
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IIC_FIST>;
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}
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// FISTTP requires SSE3 even though it's a FPStack op.
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@ -466,17 +482,23 @@ def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
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} // Predicates = [HasSSE3]
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let mayStore = 1 in {
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def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
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def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
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def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst",
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IIC_FST>;
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def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst",
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IIC_FST>;
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def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
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"fisttp{ll}\t$dst">;
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"fisttp{ll}\t$dst", IIC_FST>;
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}
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// FP Stack manipulation instructions.
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def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
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def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
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def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
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def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
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def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op",
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IIC_FLD>, D9;
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def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op",
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IIC_FST>, DD;
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def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op",
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IIC_FST>, DD;
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def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op",
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IIC_FXCH>, D9;
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// Floating point constant loads.
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let isReMaterializable = 1 in {
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@ -494,8 +516,8 @@ def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
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[(set RFP80:$dst, fpimm1)]>;
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}
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def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
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def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
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def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz", IIC_FLDZ>, D9;
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def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1", IIC_FIST>, D9;
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// Floating point compares.
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@ -520,89 +542,91 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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let Defs = [FPSW], Uses = [ST0] in {
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def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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"fucom\t$reg">, DD;
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"fucom\t$reg", IIC_FUCOM>, DD;
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def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg),
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"fucomp\t$reg">, DD;
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"fucomp\t$reg", IIC_FUCOM>, DD;
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def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
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(outs), (ins),
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"fucompp">, DA;
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"fucompp", IIC_FUCOM>, DA;
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}
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let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
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def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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"fucomi\t$reg">, DB;
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"fucomi\t$reg", IIC_FUCOMI>, DB;
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def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg),
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"fucompi\t$reg">, DF;
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"fucompi\t$reg", IIC_FUCOMI>, DF;
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}
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let Defs = [EFLAGS, FPSW] in {
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def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcomi\t$reg">, DB;
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"fcomi\t$reg", IIC_FCOMI>, DB;
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def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcompi\t$reg">, DF;
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"fcompi\t$reg", IIC_FCOMI>, DF;
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}
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// Floating point flag ops.
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let Defs = [AX], Uses = [FPSW] in
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def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags
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(outs), (ins), "fnstsw %ax",
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[(set AX, (X86fp_stsw FPSW))]>, DF;
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[(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>, DF;
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def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
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(outs), (ins i16mem:$dst), "fnstcw\t$dst",
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[(X86fp_cwd_get16 addr:$dst)]>;
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[(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>;
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let mayLoad = 1 in
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def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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(outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
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(outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>;
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// FPU control instructions
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let Defs = [FPSW] in
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def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
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def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", [], IIC_FNINIT>, DB;
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def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
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"ffree\t$reg">, DD;
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"ffree\t$reg", IIC_FFREE>, DD;
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// Clear exceptions
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let Defs = [FPSW] in
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def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
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def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", [], IIC_FNCLEX>, DB;
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// Operandless floating-point instructions for the disassembler.
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def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
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def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
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def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
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def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
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def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", []>, D9;
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def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", []>, D9;
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def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", []>, D9;
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def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", []>, D9;
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def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", []>, D9;
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def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", []>, D9;
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def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", []>, D9;
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def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", []>, D9;
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def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", []>, D9;
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def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", []>, D9;
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def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", []>, D9;
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def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", []>, D9;
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def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", []>, D9;
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def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", []>, D9;
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def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", []>, D9;
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def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
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def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", []>, D9;
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def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", []>, D9;
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def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", []>, DE;
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def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", [], IIC_FNOP>, D9;
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def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", [], IIC_FXAM>, D9;
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def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", [], IIC_FLDL>, D9;
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def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", [], IIC_FLDL>, D9;
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def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", [], IIC_FLDL>, D9;
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def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", [], IIC_FLDL>, D9;
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def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", [], IIC_FLDL>, D9;
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def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", [], IIC_F2XM1>, D9;
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def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", [], IIC_FYL2X>, D9;
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def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", [], IIC_FPTAN>, D9;
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def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", [], IIC_FPATAN>, D9;
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def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", [], IIC_FXTRACT>, D9;
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def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", [], IIC_FPREM1>, D9;
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def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", [], IIC_FPSTP>, D9;
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def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", [], IIC_FPSTP>, D9;
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def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", [], IIC_FPREM>, D9;
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def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>, D9;
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def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", [], IIC_FSINCOS>, D9;
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def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", [], IIC_FRNDINT>, D9;
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def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", [], IIC_FSCALE>, D9;
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def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", [], IIC_FCOMPP>, DE;
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def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
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"fxsave\t$dst", []>, TB;
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"fxsave\t$dst", [], IIC_FXSAVE>, TB;
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def FXSAVE64 : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
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"fxsaveq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
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"fxsaveq\t$dst", [], IIC_FXSAVE>, TB, REX_W,
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Requires<[In64BitMode]>;
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def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
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"fxrstor\t$src", []>, TB;
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"fxrstor\t$src", [], IIC_FXRSTOR>, TB;
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def FXRSTOR64 : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
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"fxrstorq\t$src", []>, TB, REX_W, Requires<[In64BitMode]>;
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"fxrstorq\t$src", [], IIC_FXRSTOR>, TB, REX_W,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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@ -255,8 +255,9 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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// FPStack Instruction Templates:
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
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: I<o, F, outs, ins, asm, []> {}
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
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InstrItinClass itin = IIC_DEFAULT>
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: I<o, F, outs, ins, asm, [], itin> {}
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// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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@ -261,6 +261,44 @@ def IIC_CMPX_LOCK_16B : InstrItinClass;
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def IIC_XADD_LOCK_MEM : InstrItinClass;
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def IIC_XADD_LOCK_MEM8 : InstrItinClass;
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def IIC_FILD : InstrItinClass;
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def IIC_FLD : InstrItinClass;
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def IIC_FLD80 : InstrItinClass;
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def IIC_FST : InstrItinClass;
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def IIC_FST80 : InstrItinClass;
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def IIC_FIST : InstrItinClass;
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def IIC_FLDZ : InstrItinClass;
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def IIC_FUCOM : InstrItinClass;
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def IIC_FUCOMI : InstrItinClass;
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def IIC_FCOMI : InstrItinClass;
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def IIC_FNSTSW : InstrItinClass;
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def IIC_FNSTCW : InstrItinClass;
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def IIC_FLDCW : InstrItinClass;
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def IIC_FNINIT : InstrItinClass;
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def IIC_FFREE : InstrItinClass;
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def IIC_FNCLEX : InstrItinClass;
|
||||
def IIC_WAIT : InstrItinClass;
|
||||
def IIC_FXAM : InstrItinClass;
|
||||
def IIC_FNOP : InstrItinClass;
|
||||
def IIC_FLDL : InstrItinClass;
|
||||
def IIC_F2XM1 : InstrItinClass;
|
||||
def IIC_FYL2X : InstrItinClass;
|
||||
def IIC_FPTAN : InstrItinClass;
|
||||
def IIC_FPATAN : InstrItinClass;
|
||||
def IIC_FXTRACT : InstrItinClass;
|
||||
def IIC_FPREM1 : InstrItinClass;
|
||||
def IIC_FPSTP : InstrItinClass;
|
||||
def IIC_FPREM : InstrItinClass;
|
||||
def IIC_FYL2XP1 : InstrItinClass;
|
||||
def IIC_FSINCOS : InstrItinClass;
|
||||
def IIC_FRNDINT : InstrItinClass;
|
||||
def IIC_FSCALE : InstrItinClass;
|
||||
def IIC_FCOMPP : InstrItinClass;
|
||||
def IIC_FXSAVE : InstrItinClass;
|
||||
def IIC_FXRSTOR : InstrItinClass;
|
||||
|
||||
def IIC_FXCH : InstrItinClass;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor instruction itineraries.
|
||||
|
||||
@ -300,6 +300,46 @@ def AtomItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_FILD, [InstrStage<5, [Port0], 0>, InstrStage<5, [Port1]>] >,
|
||||
InstrItinData<IIC_FLD, [InstrStage<1, [Port0]>] >,
|
||||
InstrItinData<IIC_FLD80, [InstrStage<4, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_FST, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FIST, [InstrStage<6, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_FLDZ, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FUCOM, [InstrStage<1, [Port1]>] >,
|
||||
InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FCOMI, [InstrStage<9, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FNSTSW, [InstrStage<10, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FNSTCW, [InstrStage<8, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FLDCW, [InstrStage<5, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FNINIT, [InstrStage<63, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FFREE, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FNCLEX, [InstrStage<25, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_WAIT, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FXAM, [InstrStage<1, [Port0]>] >,
|
||||
InstrItinData<IIC_FNOP, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FLDL, [InstrStage<10, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_F2XM1, [InstrStage<99, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FYL2X, [InstrStage<146, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FPTAN, [InstrStage<168, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FPATAN, [InstrStage<183, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FXTRACT, [InstrStage<25, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FPREM1, [InstrStage<71, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FPSTP, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FPREM, [InstrStage<55, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FYL2XP1, [InstrStage<147, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FSINCOS, [InstrStage<174, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FRNDINT, [InstrStage<46, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FSCALE, [InstrStage<77, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FCOMPP, [InstrStage<1, [Port1]>] >,
|
||||
InstrItinData<IIC_FXSAVE, [InstrStage<140, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FXRSTOR, [InstrStage<141, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >
|
||||
|
||||
]>;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user