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AVX doesn't support mm operations neither its instrinsics.

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The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-09-03 02:08:45 +00:00
parent 4b0c9f3e73
commit 95f1e2d6b5
2 changed files with 32 additions and 56 deletions
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64
lib/Target/X86/X86InstrSSE.td
View File

@ -3532,10 +3532,9 @@ let Constraints = "$src1 = $dst" in {
// SSSE3 - Packed Absolute Instructions
//===---------------------------------------------------------------------===//
/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
PatFrag mem_frag64, PatFrag mem_frag128,
Intrinsic IntId64, Intrinsic IntId128> {
/// SS3I_unop_rm_int_mm - Simple SSSE3 unary whose type can be v*{i8,i16,i32}.
multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
PatFrag mem_frag64, Intrinsic IntId64> {
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR64:$dst, (IntId64 VR64:$src))]>;
@ -3544,7 +3543,11 @@ multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR64:$dst,
(IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
}
/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
PatFrag mem_frag128, Intrinsic IntId128> {
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
@ -3560,26 +3563,28 @@ multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
}
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
int_x86_ssse3_pabs_b,
defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
int_x86_ssse3_pabs_b_128>, VEX;
defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
int_x86_ssse3_pabs_w,
defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
int_x86_ssse3_pabs_w_128>, VEX;
defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
int_x86_ssse3_pabs_d,
defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
int_x86_ssse3_pabs_d_128>, VEX;
}
defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
int_x86_ssse3_pabs_b,
int_x86_ssse3_pabs_b_128>;
defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
int_x86_ssse3_pabs_w,
int_x86_ssse3_pabs_w_128>;
defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
int_x86_ssse3_pabs_d,
int_x86_ssse3_pabs_d_128>;
defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
int_x86_ssse3_pabs_b_128>,
SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8,
int_x86_ssse3_pabs_b>;
defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
int_x86_ssse3_pabs_w_128>,
SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16,
int_x86_ssse3_pabs_w>;
defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
int_x86_ssse3_pabs_d_128>,
SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32,
int_x86_ssse3_pabs_d>;
//===---------------------------------------------------------------------===//
// SSSE3 - Packed Binary Operator Instructions
@ -3716,22 +3721,16 @@ def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
// SSSE3 - Packed Align Instruction Patterns
//===---------------------------------------------------------------------===//
multiclass sse3_palign<string asm, bit Is2Addr = 1> {
multiclass ssse3_palign_mm<string asm> {
def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2, i8imm:$src3),
!if(Is2Addr,
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
!strconcat(asm,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
[]>;
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
!if(Is2Addr,
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
!strconcat(asm,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
[]>;
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
}
multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
!if(Is2Addr,
@ -3749,9 +3748,10 @@ multiclass sse3_palign<string asm, bit Is2Addr = 1> {
}
let isAsmParserOnly = 1, Predicates = [HasAVX] in
defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
let Constraints = "$src1 = $dst" in
defm PALIGN : sse3_palign<"palignr">;
defm PALIGN : ssse3_palign<"palignr">,
ssse3_palign_mm<"palignr">;
let AddedComplexity = 5 in {

24
test/CodeGen/X86/avx-intrinsics-x86.ll
View File

@ -1715,14 +1715,6 @@ define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @test_x86_ssse3_pabs_b(<8 x i8> %a0) {
; CHECK: vpabsb
%res = call <8 x i8> @llvm.x86.ssse3.pabs.b(<8 x i8> %a0) ; <<8 x i8>> [#uses=1]
ret <8 x i8> %res
}
declare <8 x i8> @llvm.x86.ssse3.pabs.b(<8 x i8>) nounwind readnone
define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) {
; CHECK: vpabsb
%res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1]
@ -1731,14 +1723,6 @@ define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) {
declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
define <2 x i32> @test_x86_ssse3_pabs_d(<2 x i32> %a0) {
; CHECK: vpabsd
%res = call <2 x i32> @llvm.x86.ssse3.pabs.d(<2 x i32> %a0) ; <<2 x i32>> [#uses=1]
ret <2 x i32> %res
}
declare <2 x i32> @llvm.x86.ssse3.pabs.d(<2 x i32>) nounwind readnone
define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) {
; CHECK: vpabsd
%res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1]
@ -1747,14 +1731,6 @@ define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) {
declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
define <4 x i16> @test_x86_ssse3_pabs_w(<4 x i16> %a0) {
; CHECK: vpabsw
%res = call <4 x i16> @llvm.x86.ssse3.pabs.w(<4 x i16> %a0) ; <<4 x i16>> [#uses=1]
ret <4 x i16> %res
}
declare <4 x i16> @llvm.x86.ssse3.pabs.w(<4 x i16>) nounwind readnone
define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) {
; CHECK: vpabsw
%res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]