6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-05 17:39:16 +00:00
Code Issues Projects Releases Wiki Activity

PPC: Allow partial fills in writeNopData()

Browse Source 
When asked to pad an irregular number of bytes, we should fill with
zeros.  This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.

N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate.  If that behavior is needed,
we can change writeNopData() to behave in the same way.

This fixes PR17352.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2013-09-26 09:18:48 +00:00
parent 6b4e9ba218
commit 9637da6083
2 changed files with 11 additions and 5 deletions
lib/Target/PowerPC/MCTargetDesc
PPCAsmBackend.cpp
test/MC/PowerPC
ppc-nop.s

11
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

@ -132,14 +132,17 @@ public:
}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
// Can't emit NOP with size not multiple of 32-bits
if (Count % 4 != 0)
return false;
uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
OW->Write32(0x60000000);
switch (Count % 4) {
default: break; // No leftover bytes to write
case 1: OW->Write8(0); break;
case 2: OW->Write16(0); break;
case 3: OW->Write16(0); OW->Write8(0); break;
}
return true;
}

5
test/MC/PowerPC/ppc-nop.s

@ -5,5 +5,8 @@ blr
.p2align 3
blr
# CHECK: 0000: 4E800020 60000000 4E800020
.byte 0x42
.p2align 2
# CHECK: 0000: 4E800020 60000000 4E800020 42000000