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Merging r238147:

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r238147 | thomas.stellard | 2015-05-25 12:15:54 -0400 (Mon, 25 May 2015) | 4 lines

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

The src and dst register cannot be the same on chips with 16 lds banks.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240285 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard committed 2015-06-22 14:58:20 +00:00
1 parent d85ee907ff
commit 9638ce5c6d
6 files changed
+102 -20
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test/CodeGen/R600/llvm.SI.fs.interp.ll
+36 -8
View File
@@ -1,11 +1,12 @@
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;CHECK-NOT: s_wqm
;CHECK: s_mov_b32
;CHECK: v_interp_p1_f32
;CHECK: v_interp_p2_f32
;CHECK: v_interp_mov_f32
;GCN-NOT: s_wqm
;GCN: s_mov_b32
;GCN: v_interp_p1_f32
;GCN: v_interp_p2_f32
;GCN: v_interp_mov_f32
define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
main_body:
@@ -16,7 +17,33 @@ main_body:
ret void
}
declare void @llvm.AMDGPU.shader.type(i32)
; Thest that v_interp_p1 uses different source and destination registers
; on 16 bank LDS chips.
; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
main_body:
%22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
%23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
%24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
%25 = call float @fabs(float %22)
%26 = call float @fabs(float %23)
%27 = call float @fabs(float %24)
%28 = call i32 @llvm.SI.packf16(float %25, float %26)
%29 = bitcast i32 %28 to float
%30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
%31 = bitcast i32 %30 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
ret void
}
; Function Attrs: readnone
declare float @fabs(float) #2
; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1
; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1
@@ -28,3 +55,4 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float
attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }