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Rewrite MachineOperand::print and MachineInstr::print to avoid

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uses of TM->getSubtargetImpl and propagate to all calls.

This could be a debugging regression in places where we had a
TargetMachine and/or MachineFunction but don't have it as part
of the MachineInstr. Fixing this would require passing a
MachineFunction/Function down through the print operator, but
none of the existing uses in tree seem to do this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230710 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2015-02-27 00:11:34 +00:00
parent fc0ad8d28d
commit 9656d2d2bc
9 changed files with 36 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
lib/CodeGen/MachineInstr.cpp
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@@ -276,17 +276,8 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
/// print - Print the specified machine operand.
///
void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
// If the instruction is embedded into a basic block, we can find the
// target info for the instruction.
if (!TM)
if (const MachineInstr *MI = getParent())
if (const MachineBasicBlock *MBB = MI->getParent())
if (const MachineFunction *MF = MBB->getParent())
TM = &MF->getTarget();
const TargetRegisterInfo *TRI =
TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr;
void MachineOperand::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) const {
switch (getType()) {
case MachineOperand::MO_Register:
OS << PrintReg(getReg(), TRI, getSubReg());
@@ -1512,17 +1503,19 @@ void MachineInstr::dump() const {
#endif
}
void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
bool SkipOpers) const {
// We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
// We can be a bit tidier if we know the MachineFunction.
const MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
const MachineRegisterInfo *MRI = nullptr;
const TargetInstrInfo *TII = nullptr;
if (const MachineBasicBlock *MBB = getParent()) {
MF = MBB->getParent();
if (!TM && MF)
TM = &MF->getTarget();
if (MF)
if (MF) {
MRI = &MF->getRegInfo();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
}
}
// Save a list of virtual registers.
@@ -1535,7 +1528,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
!getOperand(StartOp).isImplicit();
++StartOp) {
if (StartOp != 0) OS << ", ";
getOperand(StartOp).print(OS, TM);
getOperand(StartOp).print(OS, TRI);
unsigned Reg = getOperand(StartOp).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
VirtRegs.push_back(Reg);
@@ -1545,8 +1538,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
OS << " = ";
// Print the opcode name.
if (TM && TM->getSubtargetImpl()->getInstrInfo())
OS << TM->getSubtargetImpl()->getInstrInfo()->getName(getOpcode());
if (TII)
OS << TII->getName(getOpcode());
else
OS << "UNKNOWN";
@@ -1562,7 +1555,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
// Print asm string.
OS << " ";
getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
getOperand(InlineAsm::MIOp_AsmString).print(OS, TRI);
// Print HasSideEffects, MayLoad, MayStore, IsAlignStack
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
@@ -1600,9 +1593,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
if (MRI->use_empty(Reg)) {
bool HasAliasLive = false;
for (MCRegAliasIterator AI(
Reg, TM->getSubtargetImpl()->getRegisterInfo(), true);
AI.isValid(); ++AI) {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
unsigned AliasReg = *AI;
if (!MRI->use_empty(AliasReg)) {
HasAliasLive = true;
@@ -1635,10 +1626,9 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (DI.isVariable() && !DIV.getName().empty())
OS << "!\"" << DIV.getName() << '\"';
else
MO.print(OS, TM);
} else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
OS << TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIndexName(
MO.getImm());
MO.print(OS, TRI);
} else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
OS << TRI->getSubRegIndexName(MO.getImm());
} else if (i == AsmDescOp && MO.isImm()) {
// Pretty print the inline asm operand descriptor.
OS << '$' << AsmOpCount++;
@@ -1655,11 +1645,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
unsigned RCID = 0;
if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
if (TM) {
const TargetRegisterInfo *TRI =
TM->getSubtargetImpl()->getRegisterInfo();
OS << ':'
<< TRI->getRegClassName(TRI->getRegClass(RCID));
if (TRI) {
OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
} else
OS << ":RC" << RCID;
}
@@ -1673,7 +1660,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
// Compute the index of the next operand descriptor.
AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
} else
MO.print(OS, TM);
MO.print(OS, TRI);
}
// Briefly indicate whether any call clobbers were omitted.
@@ -1709,7 +1696,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (!HaveSemi) OS << ";"; HaveSemi = true;
for (unsigned i = 0; i != VirtRegs.size(); ++i) {
const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
OS << " " << MRI->getTargetRegisterInfo()->getRegClassName(RC)
OS << " " << TRI->getRegClassName(RC)
<< ':' << PrintReg(VirtRegs[i]);
for (unsigned j = i+1; j != VirtRegs.size();) {
if (MRI->getRegClass(VirtRegs[j]) != RC) {