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Add missing HWEncoding to base register class.

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This change gives tblgen the information needed to fill in the
HexagonRegEncodingTable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217500 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sid Manning 2014-09-10 13:09:25 +00:00
parent 8c6dda0b7d
commit 96597a70dc
1 changed files with 10 additions and 8 deletions
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18
lib/Target/Hexagon/HexagonRegisterInfo.td
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@ -13,46 +13,48 @@
let Namespace = "Hexagon" in {
class HexagonReg<string n> : Register<n> {
class HexagonReg<bits<5> num, string n> : Register<n> {
field bits<5> Num;
let HWEncoding{4-0} = num;
}
class HexagonDoubleReg<string n, list<Register> subregs> :
class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs> :
RegisterWithSubRegs<n, subregs> {
field bits<5> Num;
let HWEncoding{4-0} = num;
}
// Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers.
class Ri<bits<5> num, string n> : HexagonReg<n> {
class Ri<bits<5> num, string n> : HexagonReg<num, n> {
let Num = num;
}
// Rf - 32-bit floating-point registers.
class Rf<bits<5> num, string n> : HexagonReg<n> {
class Rf<bits<5> num, string n> : HexagonReg<num, n> {
let Num = num;
}
// Rd - 64-bit registers.
class Rd<bits<5> num, string n, list<Register> subregs> :
HexagonDoubleReg<n, subregs> {
HexagonDoubleReg<num, n, subregs> {
let Num = num;
let SubRegs = subregs;
}
// Rp - predicate registers
class Rp<bits<5> num, string n> : HexagonReg<n> {
class Rp<bits<5> num, string n> : HexagonReg<num, n> {
let Num = num;
}
// Rc - control registers
class Rc<bits<5> num, string n> : HexagonReg<n> {
class Rc<bits<5> num, string n> : HexagonReg<num, n> {
let Num = num;
}
// Rj - aliased integer registers
class Rj<string n, Ri R>: HexagonReg<n> {
class Rj<string n, Ri R>: HexagonReg<R.Num, n> {
let Num = R.Num;
let Aliases = [R];
}