LiveRegUnits: Use *MBB for consistency and convenience.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192634 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-10-14 22:18:59 +00:00
parent ff09d7119d
commit 966772931e
3 changed files with 10 additions and 10 deletions

View File

@ -80,7 +80,7 @@ public:
void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
/// \brief Adds all registers in the live-in list of block @p BB.
void addLiveIns(const MachineBasicBlock &BB, const MCRegisterInfo &MCRI);
void addLiveIns(const MachineBasicBlock *MBB, const MCRegisterInfo &MCRI);
};
} // namespace llvm

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@ -1049,13 +1049,13 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
// Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
Redefs.init(TRI);
Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
Redefs.addLiveIns(*(NextBBI->BB), *TRI);
Redefs.addLiveIns(CvtBBI->BB, *TRI);
Redefs.addLiveIns(NextBBI->BB, *TRI);
// Compute a set of registers which must not be killed by instructions in
// BB1: This is everything live-in to BB2.
DontKill.init(TRI);
DontKill.addLiveIns(*(NextBBI->BB), *TRI);
DontKill.addLiveIns(NextBBI->BB, *TRI);
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
@ -1154,8 +1154,8 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(TRI);
Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
Redefs.addLiveIns(*(NextBBI->BB), *TRI);
Redefs.addLiveIns(CvtBBI->BB, *TRI);
Redefs.addLiveIns(NextBBI->BB, *TRI);
DontKill.clear();
@ -1284,7 +1284,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(TRI);
Redefs.addLiveIns(*(BBI1->BB), *TRI);
Redefs.addLiveIns(BBI1->BB, *TRI);
// Remove the duplicated instructions at the beginnings of both paths.
MachineBasicBlock::iterator DI1 = BBI1->BB->begin();

View File

@ -102,10 +102,10 @@ void LiveRegUnits::stepForward(const MachineInstr &MI,
}
/// Adds all registers in the live-in list of block @p BB.
void LiveRegUnits::addLiveIns(const MachineBasicBlock &BB,
void LiveRegUnits::addLiveIns(const MachineBasicBlock *MBB,
const MCRegisterInfo &MCRI) {
for (MachineBasicBlock::livein_iterator L = BB.livein_begin(),
LE = BB.livein_end(); L != LE; ++L) {
for (MachineBasicBlock::livein_iterator L = MBB->livein_begin(),
LE = MBB->livein_end(); L != LE; ++L) {
addReg(*L, MCRI);
}
}