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[PowerPC] Support absolute branches

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There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2013-06-24 11:03:33 +00:00
parent 9068d5310c
commit 9679c47a07
14 changed files with 344 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View File

@ -267,6 +267,12 @@ public:
bool isS16ImmX4() const { return Kind == Expression ||
(Kind == Immediate && isInt<16>(getImm()) &&
(getImm() & 3) == 0); }
bool isDirectBr() const { return Kind == Expression ||
(Kind == Immediate && isInt<26>(getImm()) &&
(getImm() & 3) == 0); }
bool isCondBr() const { return Kind == Expression ||
(Kind == Immediate && isInt<16>(getImm()) &&
(getImm() & 3) == 0); }
bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
bool isCCRegNumber() const { return Kind == Immediate &&
isUInt<3>(getImm()); }
@ -351,6 +357,14 @@ public:
Inst.addOperand(MCOperand::CreateExpr(getExpr()));
}
void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
if (Kind == Immediate)
Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
else
Inst.addOperand(MCOperand::CreateExpr(getExpr()));
}
StringRef getToken() const {
assert(Kind == Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length);

9
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
View File

@ -148,11 +148,14 @@ void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
// Branches can take an immediate operand. This is used by the branch
// selection pass to print .+8, an eight byte displacement from the PC.
O << ".+";
printAbsAddrOperand(MI, OpNo, O);
printAbsBranchOperand(MI, OpNo, O);
}
void PPCInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (!MI->getOperand(OpNo).isImm())
return printOperand(MI, OpNo, O);
O << (int)MI->getOperand(OpNo).getImm()*4;
}

2
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
View File

@ -51,7 +51,7 @@ public:
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);

6
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
View File

@ -34,8 +34,10 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
case PPC::fixup_ppc_nofixup:
return Value;
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_brcond14abs:
return Value & 0xfffc;
case PPC::fixup_ppc_br24:
case PPC::fixup_ppc_br24abs:
return Value & 0x3fffffc;
case PPC::fixup_ppc_half16:
return Value & 0xffff;
@ -56,7 +58,9 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
return 2;
case FK_Data_4:
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_brcond14abs:
case PPC::fixup_ppc_br24:
case PPC::fixup_ppc_br24abs:
return 4;
case FK_Data_8:
return 8;
@ -93,6 +97,8 @@ public:
// name offset bits flags
{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_br24abs", 6, 24, 0 },
{ "fixup_ppc_brcond14abs", 16, 14, 0 },
{ "fixup_ppc_half16", 0, 16, 0 },
{ "fixup_ppc_half16ds", 0, 14, 0 },
{ "fixup_ppc_tlsreg", 0, 0, 0 },

6
lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -58,9 +58,11 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
default:
llvm_unreachable("Unimplemented");
case PPC::fixup_ppc_br24:
case PPC::fixup_ppc_br24abs:
Type = ELF::R_PPC_REL24;
break;
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_brcond14abs:
Type = ELF::R_PPC_REL14;
break;
case PPC::fixup_ppc_half16:
@ -92,10 +94,10 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
} else {
switch ((unsigned)Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
case PPC::fixup_ppc_br24:
case PPC::fixup_ppc_br24abs:
Type = ELF::R_PPC_ADDR24;
break;
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_brcond14abs:
Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_
break;
case PPC::fixup_ppc_half16:

8
lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
View File

@ -25,6 +25,14 @@ enum Fixups {
/// branches.
fixup_ppc_brcond14,
/// fixup_ppc_br24abs - 24-bit absolute relocation for direct branches
/// like 'ba' and 'bla'.
fixup_ppc_br24abs,
/// fixup_ppc_brcond14abs - 14-bit absolute relocation for conditional
/// branches.
fixup_ppc_brcond14abs,
/// fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo)
/// or ha16(_foo) for instrs like 'li' or 'addis'.
fixup_ppc_half16,

28
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -48,6 +48,10 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getS16ImmEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
@ -134,6 +138,30 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
return 0;
}
unsigned PPCMCCodeEmitter::
getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_br24abs));
return 0;
}
unsigned PPCMCCodeEmitter::
getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_brcond14abs));
return 0;
}
unsigned PPCMCCodeEmitter::getS16ImmEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);

16
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -63,6 +63,9 @@ namespace {
unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getAbsDirectBrEncoding(const MachineInstr &MI,
unsigned OpNo) const;
unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getS16ImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
@ -193,6 +196,19 @@ unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
return 0;
}
unsigned PPCCodeEmitter::getAbsDirectBrEncoding(const MachineInstr &MI,
unsigned OpNo) const {
const MachineOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
}
unsigned PPCCodeEmitter::getAbsCondBrEncoding(const MachineInstr &MI,
unsigned OpNo) const {
llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
}
unsigned PPCCodeEmitter::getS16ImmEncoding(const MachineInstr &MI,
unsigned OpNo) const {
const MachineOperand &MO = MI.getOperand(OpNo);

8
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -102,7 +102,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
"bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
}
let Uses = [RM], isCodeGenOnly = 1 in {
@ -119,7 +119,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
"bl $func($sym)\n\tnop", BrB, []>;
def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
(outs), (ins aaddr:$func),
(outs), (ins abscalltarget:$func),
"bla $func\n\tnop", BrB,
[(PPCcall_nop (i64 imm:$func))]>;
}
@ -198,7 +198,7 @@ def TCRETURNdi8 :Pseudo< (outs),
[]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
"#TC_RETURNa8 $func $offset",
[(PPCtc_return (i64 imm:$func), imm:$offset)]>;
@ -224,7 +224,7 @@ def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
"ba $dst", BrB,
[]>;

72
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -445,19 +445,43 @@ def u16imm : Operand<i32> {
let PrintMethod = "printU16ImmOperand";
let ParserMatchClass = PPCU16ImmAsmOperand;
}
def PPCDirectBrAsmOperand : AsmOperandClass {
let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
let RenderMethod = "addBranchTargetOperands";
}
def directbrtarget : Operand<OtherVT> {
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getDirectBrEncoding";
let ParserMatchClass = PPCDirectBrAsmOperand;
}
def absdirectbrtarget : Operand<OtherVT> {
let PrintMethod = "printAbsBranchOperand";
let EncoderMethod = "getAbsDirectBrEncoding";
let ParserMatchClass = PPCDirectBrAsmOperand;
}
def PPCCondBrAsmOperand : AsmOperandClass {
let Name = "CondBr"; let PredicateMethod = "isCondBr";
let RenderMethod = "addBranchTargetOperands";
}
def condbrtarget : Operand<OtherVT> {
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getCondBrEncoding";
let ParserMatchClass = PPCCondBrAsmOperand;
}
def abscondbrtarget : Operand<OtherVT> {
let PrintMethod = "printAbsBranchOperand";
let EncoderMethod = "getAbsCondBrEncoding";
let ParserMatchClass = PPCCondBrAsmOperand;
}
def calltarget : Operand<iPTR> {
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getDirectBrEncoding";
let ParserMatchClass = PPCDirectBrAsmOperand;
}
def aaddr : Operand<iPTR> {
let PrintMethod = "printAbsAddrOperand";
def abscalltarget : Operand<iPTR> {
let PrintMethod = "printAbsBranchOperand";
let EncoderMethod = "getAbsDirectBrEncoding";
let ParserMatchClass = PPCDirectBrAsmOperand;
}
def PPCCRBitMaskOperand : AsmOperandClass {
let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
@ -872,6 +896,8 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
"b $dst", BrB,
[(br bb:$dst)]>;
def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
"ba $dst", BrB, []>;
}
// BCC represents an arbitrary conditional branch on a predicate.
@ -881,6 +907,9 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
"b${cond:cc} ${cond:reg}, $dst"
/*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
"b${cond:cc}a ${cond:reg}, $dst">;
let isReturn = 1, Uses = [LR, RM] in
def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
"b${cond:cc}lr ${cond:reg}", BrB, []>;
@ -898,6 +927,10 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
"bdz $dst">;
def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
"bdnz $dst">;
def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdza $dst">;
def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdnza $dst">;
}
}
@ -914,12 +947,15 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
let Uses = [RM] in {
def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
"bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
let isCodeGenOnly = 1 in
def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
"b${cond:cc}l ${cond:reg}, $dst">;
let isCodeGenOnly = 1 in {
def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
"b${cond:cc}l ${cond:reg}, $dst">;
def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
"b${cond:cc}la ${cond:reg}, $dst">;
}
}
let Uses = [CTR, RM] in {
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
@ -943,6 +979,10 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
"bdzl $dst">;
def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
"bdnzl $dst">;
def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdzla $dst">;
def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdnzla $dst">;
}
let Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
@ -960,7 +1000,7 @@ def TCRETURNdi :Pseudo< (outs),
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
"#TC_RETURNa $func $offset",
[(PPCtc_return (i32 imm:$func), imm:$offset)]>;
@ -977,22 +1017,20 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
Requires<[In32BitMode]>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
"b $dst", BrB,
[]>;
}
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
"ba $dst", BrB,
[]>;
}
let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
"#EH_SJLJ_SETJMP32",
@ -2197,6 +2235,11 @@ multiclass BranchExtendedMnemonic<string name, int bibo> {
def : InstAlias<"b"#name#" $dst",
(BCC bibo, CR0, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"a $cc, $dst",
(BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"a $dst",
(BCCA bibo, CR0, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lr $cc",
(BCLR bibo, crrc:$cc)>;
def : InstAlias<"b"#name#"lr",
@ -2212,6 +2255,11 @@ multiclass BranchExtendedMnemonic<string name, int bibo> {
def : InstAlias<"b"#name#"l $dst",
(BCCL bibo, CR0, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"la $cc, $dst",
(BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"la $dst",
(BCCLA bibo, CR0, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lrl $cc",
(BCLRL bibo, crrc:$cc)>;
def : InstAlias<"b"#name#"lrl",

208
test/MC/PowerPC/ppc64-encoding-ext.s
View File

@ -51,13 +51,17 @@
# CHECK: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnz target
# FIXME: bdnza target
# CHECK: bdnza target # encoding: [0x42,0x00,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnza target
# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20]
bdnzlr
# CHECK: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzl target
# FIXME: bdnzla target
# CHECK: bdnzla target # encoding: [0x42,0x00,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzla target
# CHECK: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21]
bdnzlrl
@ -89,13 +93,17 @@
# CHECK: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdz target
# FIXME: bdza target
# CHECK: bdza target # encoding: [0x42,0x40,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdza target
# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20]
bdzlr
# CHECK: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzl target
# FIXME: bdzla target
# CHECK: bdzla target # encoding: [0x42,0x40,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzla target
# CHECK: bdzlrl # encoding: [0x4e,0x40,0x00,0x21]
bdzlrl
@ -130,8 +138,12 @@
# CHECK: blt 0, target # encoding: [0x41,0x80,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt target
# FIXME: blta 2, target
# FIXME: blta target
# CHECK: blta 2, target # encoding: [0x41,0x88,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta 2, target
# CHECK: blta 0, target # encoding: [0x41,0x80,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta target
# CHECK: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20]
bltlr 2
# CHECK: bltlr 0 # encoding: [0x4d,0x80,0x00,0x20]
@ -146,8 +158,12 @@
# CHECK: bltl 0, target # encoding: [0x41,0x80,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl target
# FIXME: bltla 2, target
# FIXME: bltla target
# CHECK: bltla 2, target # encoding: [0x41,0x88,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla 2, target
# CHECK: bltla 0, target # encoding: [0x41,0x80,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla target
# CHECK: bltlrl 2 # encoding: [0x4d,0x88,0x00,0x21]
bltlrl 2
# CHECK: bltlrl 0 # encoding: [0x4d,0x80,0x00,0x21]
@ -163,8 +179,12 @@
# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble target
# FIXME: blea 2, target
# FIXME: blea target
# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea 2, target
# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea target
# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
blelr 2
# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20]
@ -179,8 +199,12 @@
# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel target
# FIXME: blela 2, target
# FIXME: blela target
# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela 2, target
# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela target
# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21]
blelrl 2
# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21]
@ -196,8 +220,12 @@
# CHECK: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq target
# FIXME: beqa 2, target
# FIXME: beqa target
# CHECK: beqa 2, target # encoding: [0x41,0x8a,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa 2, target
# CHECK: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa target
# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20]
beqlr 2
# CHECK: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20]
@ -212,8 +240,12 @@
# CHECK: beql 0, target # encoding: [0x41,0x82,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql target
# FIXME: beqla 2, target
# FIXME: beqla target
# CHECK: beqla 2, target # encoding: [0x41,0x8a,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla 2, target
# CHECK: beqla 0, target # encoding: [0x41,0x82,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla target
# CHECK: beqlrl 2 # encoding: [0x4d,0x8a,0x00,0x21]
beqlrl 2
# CHECK: beqlrl 0 # encoding: [0x4d,0x82,0x00,0x21]
@ -229,8 +261,12 @@
# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge target
# FIXME: bgea 2, target
# FIXME: bgea target
# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea 2, target
# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea target
# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
bgelr 2
# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20]
@ -245,8 +281,12 @@
# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel target
# FIXME: bgela 2, target
# FIXME: bgela target
# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela 2, target
# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela target
# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21]
bgelrl 2
# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21]
@ -262,8 +302,12 @@
# CHECK: bgt 0, target # encoding: [0x41,0x81,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt target
# FIXME: bgta 2, target
# FIXME: bgta target
# CHECK: bgta 2, target # encoding: [0x41,0x89,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta 2, target
# CHECK: bgta 0, target # encoding: [0x41,0x81,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta target
# CHECK: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20]
bgtlr 2
# CHECK: bgtlr 0 # encoding: [0x4d,0x81,0x00,0x20]
@ -278,8 +322,12 @@
# CHECK: bgtl 0, target # encoding: [0x41,0x81,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl target
# FIXME: bgtla 2, target
# FIXME: bgtla target
# CHECK: bgtla 2, target # encoding: [0x41,0x89,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla 2, target
# CHECK: bgtla 0, target # encoding: [0x41,0x81,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla target
# CHECK: bgtlrl 2 # encoding: [0x4d,0x89,0x00,0x21]
bgtlrl 2
# CHECK: bgtlrl 0 # encoding: [0x4d,0x81,0x00,0x21]
@ -295,8 +343,12 @@
# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl target
# FIXME: bnla 2, target
# FIXME: bnla target
# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla 2, target
# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla target
# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
bnllr 2
# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20]
@ -311,8 +363,12 @@
# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll target
# FIXME: bnlla 2, target
# FIXME: bnlla target
# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla 2, target
# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla target
# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21]
bnllrl 2
# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21]
@ -328,8 +384,12 @@
# CHECK: bne 0, target # encoding: [0x40,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne target
# FIXME: bnea 2, target
# FIXME: bnea target
# CHECK: bnea 2, target # encoding: [0x40,0x8a,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea 2, target
# CHECK: bnea 0, target # encoding: [0x40,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea target
# CHECK: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20]
bnelr 2
# CHECK: bnelr 0 # encoding: [0x4c,0x82,0x00,0x20]
@ -344,8 +404,12 @@
# CHECK: bnel 0, target # encoding: [0x40,0x82,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel target
# FIXME: bnela 2, target
# FIXME: bnela target
# CHECK: bnela 2, target # encoding: [0x40,0x8a,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela 2, target
# CHECK: bnela 0, target # encoding: [0x40,0x82,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela target
# CHECK: bnelrl 2 # encoding: [0x4c,0x8a,0x00,0x21]
bnelrl 2
# CHECK: bnelrl 0 # encoding: [0x4c,0x82,0x00,0x21]
@ -361,8 +425,12 @@
# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng target
# FIXME: bnga 2, target
# FIXME: bnga target
# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga 2, target
# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga target
# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
bnglr 2
# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20]
@ -377,8 +445,12 @@
# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl target
# FIXME: bngla 2, target
# FIXME: bngla target
# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla 2, target
# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla target
# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21]
bnglrl 2
# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21]
@ -394,8 +466,12 @@
# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso target
# FIXME: bsoa 2, target
# FIXME: bsoa target
# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa 2, target
# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa target
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
bsolr 2
# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20]
@ -410,8 +486,12 @@
# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol target
# FIXME: bsola 2, target
# FIXME: bsola target
# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola 2, target
# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola target
# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21]
bsolrl 2
# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21]
@ -427,8 +507,12 @@
# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns target
# FIXME: bnsa 2, target
# FIXME: bnsa target
# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa 2, target
# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa target
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
bnslr 2
# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20]
@ -443,8 +527,12 @@
# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl target
# FIXME: bnsla 2, target
# FIXME: bnsla target
# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla 2, target
# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla target
# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21]
bnslrl 2
# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21]
@ -460,8 +548,12 @@
# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun target
# FIXME: buna 2, target
# FIXME: buna target
# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna 2, target
# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna target
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
bunlr 2
# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20]
@ -476,8 +568,12 @@
# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl target
# FIXME: bunla 2, target
# FIXME: bunla target
# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla 2, target
# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla target
# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21]
bunlrl 2
# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21]
@ -493,8 +589,12 @@
# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu target
# FIXME: bnua 2, target
# FIXME: bnua target
# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua 2, target
# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua target
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
bnulr 2
# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20]
@ -509,8 +609,12 @@
# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul target
# FIXME: bnula 2, target
# FIXME: bnula target
# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula 2, target
# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula target
# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21]
bnulrl 2
# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21]

8
test/MC/PowerPC/ppc64-encoding.s
View File

@ -8,11 +8,15 @@
# CHECK: b target # encoding: [0b010010AA,A,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24
b target
# FIXME: ba target
# CHECK: ba target # encoding: [0b010010AA,A,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
ba target
# CHECK: bl target # encoding: [0b010010AA,A,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24
bl target
# FIXME: bla target
# CHECK: bla target # encoding: [0b010010AA,A,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
bla target
# FIXME: bc 4, 10, target
# FIXME: bca 4, 10, target

20
test/MC/PowerPC/ppc64-fixups.s
View File

@ -4,6 +4,26 @@
# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \
# RUN: llvm-readobj -r | FileCheck %s -check-prefix=REL
# CHECK: b target # encoding: [0b010010AA,A,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24
# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 target 0x0
b target
# CHECK: ba target # encoding: [0b010010AA,A,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR24 target 0x0
ba target
# CHECK: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL14 target 0x0
beq target
# CHECK: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR14 target 0x0
beqa target
# FIXME: .TOC.@tocbase

15
test/MC/PowerPC/ppc64-operands.s
View File

@ -85,3 +85,18 @@
# CHECK: ld 1, -4(2) # encoding: [0xe8,0x22,0xff,0xfc]
ld 1, -4(2)
# Immediate branch operands
# CHECK: b .+1024 # encoding: [0x48,0x00,0x04,0x00]
b 1024
# CHECK: ba 1024 # encoding: [0x48,0x00,0x04,0x02]
ba 1024
# CHECK: beq 0, .+1024 # encoding: [0x41,0x82,0x04,0x00]
beq 1024
# CHECK: beqa 0, 1024 # encoding: [0x41,0x82,0x04,0x02]
beqa 1024