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R600/SI: Add instruction shrinking pass

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This pass converts 64-bit instructions to 32-bit when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-07-21 16:55:33 +00:00
parent cef5388ce8
commit 9787e8c76b
13 changed files with 223 additions and 5 deletions
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9
lib/Target/R600/SIInstrInfo.cpp
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@@ -1639,3 +1639,12 @@ void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
}
const MachineOperand *SIInstrInfo::getNamedOperand(const MachineInstr& MI,
unsigned OperandName) const {
int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
if (Idx == -1)
return nullptr;
return &MI.getOperand(Idx);
}