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Dont' set flags

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-11-21 01:59:50 +00:00
parent 233ad71051
commit 97ad9e1fea
2 changed files with 10 additions and 16 deletions
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13
lib/Target/X86/InstSelectSimple.cpp
View File

@@ -240,7 +240,7 @@ ISel::visitSetCondInst (SetCondInst & I)
// Move fp status word (concodes) to ax. // Move fp status word (concodes) to ax.
BuildMI (BB, X86::FNSTSWr8, 1, X86::AX); BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
// Load real concodes from ax. // Load real concodes from ax.
BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH); BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
} }
else else
{ // integer comparison { // integer comparison
@@ -250,16 +250,13 @@ ISel::visitSetCondInst (SetCondInst & I)
switch (comparisonWidth) switch (comparisonWidth)
{ {
case 1: case 1:
BuildMI (BB, X86::CMPrr8, 2, BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
X86::EFLAGS).addReg (reg1).addReg (reg2);
break; break;
case 2: case 2:
BuildMI (BB, X86::CMPrr16, 2, BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
X86::EFLAGS).addReg (reg1).addReg (reg2);
break; break;
case 4: case 4:
BuildMI (BB, X86::CMPrr32, 2, BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
X86::EFLAGS).addReg (reg1).addReg (reg2);
break; break;
case 8: case 8:
default: default:
@@ -413,7 +410,7 @@ ISel::visitBranchInst (BranchInst & BI)
// followed by jump-if-equal to ifFalse, and jump-if-nonequal to // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
// ifTrue // ifTrue
unsigned int condReg = getReg (BI.getCondition ()); unsigned int condReg = getReg (BI.getCondition ());
BuildMI (BB, X86::CMPri8, 2, X86::EFLAGS).addReg (condReg).addZImm (0); BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0)); BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1)); BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
} }

13
lib/Target/X86/X86ISelSimple.cpp
View File

@@ -240,7 +240,7 @@ ISel::visitSetCondInst (SetCondInst & I)
// Move fp status word (concodes) to ax. // Move fp status word (concodes) to ax.
BuildMI (BB, X86::FNSTSWr8, 1, X86::AX); BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
// Load real concodes from ax. // Load real concodes from ax.
BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH); BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
} }
else else
{ // integer comparison { // integer comparison
@@ -250,16 +250,13 @@ ISel::visitSetCondInst (SetCondInst & I)
switch (comparisonWidth) switch (comparisonWidth)
{ {
case 1: case 1:
BuildMI (BB, X86::CMPrr8, 2, BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
X86::EFLAGS).addReg (reg1).addReg (reg2);
break; break;
case 2: case 2:
BuildMI (BB, X86::CMPrr16, 2, BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
X86::EFLAGS).addReg (reg1).addReg (reg2);
break; break;
case 4: case 4:
BuildMI (BB, X86::CMPrr32, 2, BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
X86::EFLAGS).addReg (reg1).addReg (reg2);
break; break;
case 8: case 8:
default: default:
@@ -413,7 +410,7 @@ ISel::visitBranchInst (BranchInst & BI)
// followed by jump-if-equal to ifFalse, and jump-if-nonequal to // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
// ifTrue // ifTrue
unsigned int condReg = getReg (BI.getCondition ()); unsigned int condReg = getReg (BI.getCondition ());
BuildMI (BB, X86::CMPri8, 2, X86::EFLAGS).addReg (condReg).addZImm (0); BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0)); BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1)); BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
} }