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removed some debug messages

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@910 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
2001-10-18 22:36:26 +00:00
parent f8f2afb8cc
commit 97b8b4410a
2 changed files with 34 additions and 30 deletions
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22
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@@ -256,7 +256,7 @@ void PhyRegAlloc::addInterferencesForArgs()
addInterference( *ArgIt, InSet, false ); // add interferences between addInterference( *ArgIt, InSet, false ); // add interferences between
// args and LVars at start // args and LVars at start
if( DEBUG_RA > 1) { if( DEBUG_RA > 1) {
cout << " - %% adding interference for argument "; cout << " - %% adding interference for argument ";
printValue( (const Value *) *ArgIt); cout << endl; printValue( (const Value *) *ArgIt); cout << endl;
} }
} }
@@ -350,8 +350,12 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
PushedRegSet.insert( Reg ); PushedRegSet.insert( Reg );
StackOff -= 8; // ****TODO: Correct ?????? StackOff -= 8; // ****TODO: Correct ??????
cerr << "\n $$$ Inserted caller saving instr";
if(DEBUG_RA) {
cout << "For callee save call inst:" << *MInst << endl;
cerr << "\n -inserted caller saving instrs:\n\t ";
cerr << *AdIBef << "\n\t" << *AdIAft ;
}
} // if not already pushed } // if not already pushed
} // if LR has a volatile color } // if LR has a volatile color
@@ -405,9 +409,8 @@ void PhyRegAlloc::updateMachineCode()
for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) { for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
cerr << " *$* PREPENDed instr opcode: "; if( DEBUG_RA)
cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString; cerr << " *$* PREPENDed instr " << *AdIt << endl;
cerr << endl;
MInstIterator = MIVec.insert( MInstIterator, *AdIt ); MInstIterator = MIVec.insert( MInstIterator, *AdIt );
++MInstIterator; ++MInstIterator;
@@ -513,9 +516,8 @@ void PhyRegAlloc::updateMachineCode()
for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) { for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
cerr << " *#* APPENDed instr opcode: "; if(DEBUG_RA)
cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString; cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
cerr << endl;
MInstIterator = MIVec.insert( MInstIterator, *AdIt ); MInstIterator = MIVec.insert( MInstIterator, *AdIt );
++MInstIterator; ++MInstIterator;
@@ -574,8 +576,8 @@ void PhyRegAlloc::printMachineCode()
MachineOperand& Op = MInst->getOperand(OpNum); MachineOperand& Op = MInst->getOperand(OpNum);
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister || if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister || Op.getOperandType() == MachineOperand::MO_CCRegister /*||
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) { Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
const Value *const Val = Op.getVRegValue () ; const Value *const Val = Op.getVRegValue () ;
// ****this code is temporary till NULL Values are fixed // ****this code is temporary till NULL Values are fixed

22
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@@ -256,7 +256,7 @@ void PhyRegAlloc::addInterferencesForArgs()
addInterference( *ArgIt, InSet, false ); // add interferences between addInterference( *ArgIt, InSet, false ); // add interferences between
// args and LVars at start // args and LVars at start
if( DEBUG_RA > 1) { if( DEBUG_RA > 1) {
cout << " - %% adding interference for argument "; cout << " - %% adding interference for argument ";
printValue( (const Value *) *ArgIt); cout << endl; printValue( (const Value *) *ArgIt); cout << endl;
} }
} }
@@ -350,8 +350,12 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
PushedRegSet.insert( Reg ); PushedRegSet.insert( Reg );
StackOff -= 8; // ****TODO: Correct ?????? StackOff -= 8; // ****TODO: Correct ??????
cerr << "\n $$$ Inserted caller saving instr";
if(DEBUG_RA) {
cout << "For callee save call inst:" << *MInst << endl;
cerr << "\n -inserted caller saving instrs:\n\t ";
cerr << *AdIBef << "\n\t" << *AdIAft ;
}
} // if not already pushed } // if not already pushed
} // if LR has a volatile color } // if LR has a volatile color
@@ -405,9 +409,8 @@ void PhyRegAlloc::updateMachineCode()
for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) { for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
cerr << " *$* PREPENDed instr opcode: "; if( DEBUG_RA)
cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString; cerr << " *$* PREPENDed instr " << *AdIt << endl;
cerr << endl;
MInstIterator = MIVec.insert( MInstIterator, *AdIt ); MInstIterator = MIVec.insert( MInstIterator, *AdIt );
++MInstIterator; ++MInstIterator;
@@ -513,9 +516,8 @@ void PhyRegAlloc::updateMachineCode()
for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) { for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
cerr << " *#* APPENDed instr opcode: "; if(DEBUG_RA)
cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString; cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
cerr << endl;
MInstIterator = MIVec.insert( MInstIterator, *AdIt ); MInstIterator = MIVec.insert( MInstIterator, *AdIt );
++MInstIterator; ++MInstIterator;
@@ -574,8 +576,8 @@ void PhyRegAlloc::printMachineCode()
MachineOperand& Op = MInst->getOperand(OpNum); MachineOperand& Op = MInst->getOperand(OpNum);
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister || if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
Op.getOperandType() == MachineOperand::MO_CCRegister || Op.getOperandType() == MachineOperand::MO_CCRegister /*||
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) { Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
const Value *const Val = Op.getVRegValue () ; const Value *const Val = Op.getVRegValue () ;
// ****this code is temporary till NULL Values are fixed // ****this code is temporary till NULL Values are fixed