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Pass extra regclasses into spilling code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-09-30 01:29:42 +00:00
parent bf9716b9c4
commit 97d5e6461a
12 changed files with 49 additions and 25 deletions
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6
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@@ -75,7 +75,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void
AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (EnableAlphaLSMark)
@@ -92,7 +93,8 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
void
AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)