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Pass extra regclasses into spilling code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-09-30 01:29:42 +00:00
parent bf9716b9c4
commit 97d5e6461a
12 changed files with 49 additions and 25 deletions
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6
lib/Target/Sparc/SparcRegisterInfo.cpp
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@@ -40,7 +40,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
@@ -59,7 +60,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
void SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(DestReg);
if (RC == V8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);