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Pass extra regclasses into spilling code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-09-30 01:29:42 +00:00
parent bf9716b9c4
commit 97d5e6461a
12 changed files with 49 additions and 25 deletions
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6
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@@ -75,7 +75,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void
AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (EnableAlphaLSMark)
@@ -92,7 +93,8 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
void
AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)

6
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@@ -27,11 +27,13 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex) const;
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

6
lib/Target/Skeleton/SkeletonRegisterInfo.cpp
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@@ -22,13 +22,15 @@ SkeletonRegisterInfo::SkeletonRegisterInfo()
void SkeletonRegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
abort();
}
void SkeletonRegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIdx) const {
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
abort();
}

8
lib/Target/Skeleton/SkeletonRegisterInfo.h
View File

@@ -1,4 +1,4 @@
//===- SkeletonRegisterInfo.h - Skeleton Register Information Impl -*- C++ -*-==//
//===- SkeletonRegisterInfo.h - Skeleton Register Info Impl ------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@@ -24,11 +24,13 @@ namespace llvm {
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex) const;
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

6
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@@ -40,7 +40,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
@@ -59,7 +60,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
void SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(DestReg);
if (RC == V8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);

6
lib/Target/Sparc/SparcRegisterInfo.h
View File

@@ -28,11 +28,13 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex) const;
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

6
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
View File

@@ -40,7 +40,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
@@ -59,7 +60,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
void SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(DestReg);
if (RC == V8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);

6
lib/Target/SparcV8/SparcV8RegisterInfo.h
View File

@@ -28,11 +28,13 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex) const;
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

6
lib/Target/SparcV9/SparcV9RegisterInfo.cpp
View File

@@ -278,13 +278,15 @@ SparcV9RegisterInfo::SparcV9RegisterInfo ()
void SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex) const{
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const {
abort ();
}
void SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex) const {
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const {
abort ();
}

6
lib/Target/SparcV9/SparcV9RegisterInfo.h
View File

@@ -27,10 +27,12 @@ struct SparcV9RegisterInfo : public MRegisterInfo {
// The rest of these are stubs... for now.
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex) const;
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex) const;
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,

6
lib/Target/X86/X86RegisterInfo.cpp
View File

@@ -58,7 +58,8 @@ static unsigned getIdx(unsigned SpillSize) {
void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx) const {
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] =
{ X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST64m, X86::FSTP80m,
X86::MOVAPDmr };
@@ -70,7 +71,8 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx)const{
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
static const unsigned Opcode[] =
{ X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD64m, X86::FLD80m,
X86::MOVAPDrm };

6
lib/Target/X86/X86RegisterInfo.h
View File

@@ -28,11 +28,13 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex) const;
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex) const;
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,