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https://github.com/c64scene-ar/llvm-6502.git
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Use a better idiom to silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51131 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -406,11 +406,8 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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// Just use the input register directly!
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// Just use the input register directly!
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if (InstanceNo > 0)
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if (InstanceNo > 0)
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VRBaseMap.erase(SDOperand(Node, ResNo));
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VRBaseMap.erase(SDOperand(Node, ResNo));
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#ifndef NDEBUG
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
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#else
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isNew = isNew; // Silence compiler warning.
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VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
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#endif
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assert(isNew && "Node emitted out of order - early");
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assert(isNew && "Node emitted out of order - early");
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return;
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return;
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}
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}
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@@ -468,11 +465,8 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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if (InstanceNo > 0)
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if (InstanceNo > 0)
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VRBaseMap.erase(SDOperand(Node, ResNo));
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VRBaseMap.erase(SDOperand(Node, ResNo));
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#ifndef NDEBUG
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
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#else
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isNew = isNew; // Silence compiler warning.
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VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
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#endif
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assert(isNew && "Node emitted out of order - early");
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assert(isNew && "Node emitted out of order - early");
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}
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}
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@@ -529,11 +523,8 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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}
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#ifndef NDEBUG
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
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#else
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isNew = isNew; // Silence compiler warning.
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VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
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#endif
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assert(isNew && "Node emitted out of order - early");
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assert(isNew && "Node emitted out of order - early");
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}
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}
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}
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}
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@@ -785,11 +776,8 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
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} else
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} else
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assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
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assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
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#ifndef NDEBUG
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
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#else
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isNew = isNew; // Silence compiler warning.
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VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
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#endif
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assert(isNew && "Node emitted out of order - early");
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assert(isNew && "Node emitted out of order - early");
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}
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}
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@@ -1016,11 +1004,8 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
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// Copy from physical register.
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// Copy from physical register.
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assert(I->Reg && "Unknown physical register!");
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assert(I->Reg && "Unknown physical register!");
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unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
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unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
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#ifndef NDEBUG
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bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
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bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
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#else
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isNew = isNew; // Silence compiler warning.
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VRBaseMap.insert(std::make_pair(SU, VRBase));
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#endif
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assert(isNew && "Node emitted out of order - early");
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assert(isNew && "Node emitted out of order - early");
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TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
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TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
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SU->CopyDstRC, SU->CopySrcRC);
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SU->CopyDstRC, SU->CopySrcRC);
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