mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
Encode extend instructions; more clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
e187726208
commit
97f48c39fd
@ -98,6 +98,8 @@ namespace {
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void emitMulFrmInstruction(const MachineInstr &MI);
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void emitExtendInstruction(const MachineInstr &MI);
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void emitBranchInstruction(const MachineInstr &MI);
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void emitMiscBranchInstruction(const MachineInstr &MI);
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@ -282,6 +284,9 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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case ARMII::MulFrm:
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emitMulFrmInstruction(MI);
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break;
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case ARMII::ExtFrm:
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emitExtendInstruction(MI);
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break;
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case ARMII::BrFrm:
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emitBranchInstruction(MI);
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break;
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@ -349,7 +354,7 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
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unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
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// Set the conditional execution predicate.
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Encode Rd.
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Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
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@ -364,7 +369,7 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
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Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
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// Set the conditional execution predicate.
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Encode Rd.
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Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
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@ -488,7 +493,9 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
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unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
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// Encode rotate_imm.
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unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1) << ARMII::RotImmShift;
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unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
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<< ARMII::SoRotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmValImm(SoImm);
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return Binary;
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@ -512,7 +519,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrModeSBit(MI, TID);
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@ -570,7 +577,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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@ -623,7 +630,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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@ -656,7 +663,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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}
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// This instr is in immediate offset/index encoding, set bit 22 to 1.
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Binary |= 1 << 22;
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Binary |= 1 << ARMII::AM3_I_BitShift;
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
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// Set operands
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Binary |= (ImmOffs >> 4) << 8; // immedH
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@ -671,7 +678,7 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
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@ -686,14 +693,14 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
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switch (Mode) {
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default: assert(0 && "Unknown addressing sub-mode!");
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case ARM_AM::da: break;
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case ARM_AM::db: Binary |= 0x1 << 24; break;
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case ARM_AM::ia: Binary |= 0x1 << 23; break;
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case ARM_AM::ib: Binary |= 0x3 << 23; break;
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case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
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case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
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case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
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}
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// Set bit W(21)
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if (ARM_AM::getAM4WBFlag(MO.getImm()))
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Binary |= 0x1 << 21;
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Binary |= 0x1 << ARMII::W_BitShift;
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// Set registers
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for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
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@ -716,14 +723,14 @@ void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrModeSBit(MI, TID);
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// 32x32->64bit operations have two destination registers. The number
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// of register definitions will tell us if that's what we're dealing with.
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int OpIdx = 0;
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unsigned OpIdx = 0;
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if (TID.getNumDefs() == 2)
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Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
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@ -738,8 +745,47 @@ void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
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// Many multiple instructions (e.g. MLA) have three src operands. Encode
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// it as Rn (for multiply, that's in the same offset as RdLo.
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if (TID.getNumOperands() - TID.getNumDefs() == 3)
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdLoShift;
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if (TID.getNumOperands() > OpIdx &&
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!TID.OpInfo[OpIdx].isPredicate() &&
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!TID.OpInfo[OpIdx].isOptionalDef())
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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unsigned OpIdx = 0;
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// Encode Rd
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
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const MachineOperand &MO1 = MI.getOperand(OpIdx++);
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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if (MO2.isReg()) {
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// Two register operand form.
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// Encode Rn.
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Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
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// Encode Rm.
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Binary |= getMachineOpValue(MI, MO2);
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++OpIdx;
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} else {
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Binary |= getMachineOpValue(MI, MO1);
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}
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// Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
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if (MI.getOperand(OpIdx).isImm() &&
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!TID.OpInfo[OpIdx].isPredicate() &&
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!TID.OpInfo[OpIdx].isOptionalDef())
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Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
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emitWordLE(Binary);
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}
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@ -754,17 +800,11 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Set signed_immed_24 field
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Binary |= getMachineOpValue(MI, 0);
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// if it is a conditional branch, set cond field
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if (TID.Opcode == ARM::Bcc) {
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Binary &= 0x0FFFFFFF; // clear conditional field
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Binary |= getMachineOpValue(MI, 1) << 28; // set conditional field
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}
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emitWordLE(Binary);
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}
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@ -780,7 +820,7 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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if (TID.Opcode == ARM::BX_RET)
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// The return register is LR.
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@ -34,9 +34,10 @@ def StMiscFrm : Format<10>;
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def LdMulFrm : Format<11>;
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def StMulFrm : Format<12>;
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def ArithMisc : Format<13>;
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def ThumbFrm : Format<14>;
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def VFPFrm : Format<15>;
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def ArithMiscFrm: Format<13>;
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def ExtFrm : Format<14>;
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def ThumbFrm : Format<15>;
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def VFPFrm : Format<16>;
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// Misc flag for data processing instructions that indicates whether
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// the instruction has a Rn register operand.
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@ -123,11 +124,11 @@ class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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class AI<dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>;
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asm, "", pattern>;
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class AsI<dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>;
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asm, "", pattern>;
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class AXI<dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
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@ -137,7 +138,7 @@ class AXI<dag oops, dag iops, Format f, string asm,
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class ABI<bits<4> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
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asm,"",pattern> {
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asm, "", pattern> {
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let Inst{27-24} = opcod;
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}
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class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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@ -645,7 +646,7 @@ class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
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class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
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asm,"",pattern> {
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asm, "", pattern> {
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let Inst{7-4} = 0b1001;
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let Inst{20} = 0; // S bit
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let Inst{27-21} = opcod;
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@ -653,7 +654,7 @@ class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
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class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
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asm,"",pattern> {
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asm, "", pattern> {
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let Inst{7-4} = 0b1001;
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let Inst{27-21} = opcod;
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}
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@ -662,7 +663,7 @@ class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
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class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
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asm,"",pattern> {
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asm, "", pattern> {
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let Inst{7-4} = 0b1001;
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let Inst{20} = 1;
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let Inst{27-21} = opcod;
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@ -672,13 +673,22 @@ class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
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class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
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asm,"",pattern> {
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asm, "", pattern> {
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let Inst{4} = 0;
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let Inst{7} = 1;
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let Inst{20} = 0;
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let Inst{27-21} = opcod;
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}
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// Extend instructions.
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class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
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asm, "", pattern> {
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let Inst{7-4} = 0b0111;
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let Inst{27-20} = opcod;
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}
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//===----------------------------------------------------------------------===//
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// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
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@ -95,28 +95,34 @@ namespace ARMII {
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StMulFrm = 12 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMisc = 13 << FormShift,
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ArithMiscFrm= 13 << FormShift,
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// Extend instructions
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ExtFrm = 14 << FormShift,
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// Thumb format
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ThumbFrm = 14 << FormShift,
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ThumbFrm = 15 << FormShift,
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// VFP format
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VPFFrm = 15 << FormShift,
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VPFFrm = 16 << FormShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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RotImmShift = 8,
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RegRsShift = 8,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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L_BitShift = 20,
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S_BitShift = 20,
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U_BitShift = 23,
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IndexShift = 24,
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I_BitShift = 25
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SoRotImmShift = 8,
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RegRsShift = 8,
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ExtRotImmShift = 10,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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S_BitShift = 20,
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W_BitShift = 21,
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AM3_I_BitShift = 22,
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U_BitShift = 23,
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P_BitShift = 24,
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I_BitShift = 25,
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CondShift = 28
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};
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}
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@ -390,25 +390,31 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
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/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass AI_unary_rrot<string opc, PatFrag opnode> {
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def r : AI<(outs GPR:$dst), (ins GPR:$Src), Pseudo,
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/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
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multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
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opc, " $dst, $Src",
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[(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
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def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
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[(set GPR:$dst, (opnode GPR:$Src))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{19-16} = 0b1111;
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}
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def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
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opc, " $dst, $Src, ror $rot",
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[(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]>;
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Requires<[IsARM, HasV6]> {
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let Inst{19-16} = 0b1111;
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}
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}
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/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass AI_bin_rrot<string opc, PatFrag opnode> {
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def rr : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
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Pseudo, opc, " $dst, $LHS, $RHS",
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multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
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opc, " $dst, $LHS, $RHS",
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[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
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Requires<[IsARM, HasV6]>;
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def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
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Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
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def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
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opc, " $dst, $LHS, $RHS, ror $rot",
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[(set GPR:$dst, (opnode GPR:$LHS,
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(rotr GPR:$RHS, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]>;
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@ -781,31 +787,36 @@ def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
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// Sign extenders
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defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
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||||
defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
|
||||
defm SXTB : AI_unary_rrot<0b01101010,
|
||||
"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
|
||||
defm SXTH : AI_unary_rrot<0b01101011,
|
||||
"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
|
||||
|
||||
defm SXTAB : AI_bin_rrot<"sxtab",
|
||||
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
|
||||
defm SXTAH : AI_bin_rrot<"sxtah",
|
||||
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
|
||||
defm SXTAB : AI_bin_rrot<0b01101010,
|
||||
"sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
|
||||
defm SXTAH : AI_bin_rrot<0b01101011,
|
||||
"sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
|
||||
|
||||
// TODO: SXT(A){B|H}16
|
||||
|
||||
// Zero extenders
|
||||
|
||||
let AddedComplexity = 16 in {
|
||||
defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
|
||||
defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
|
||||
defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
|
||||
defm UXTB : AI_unary_rrot<0b01101110,
|
||||
"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
|
||||
defm UXTH : AI_unary_rrot<0b01101111,
|
||||
"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
|
||||
defm UXTB16 : AI_unary_rrot<0b01101100,
|
||||
"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
|
||||
|
||||
def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
|
||||
(UXTB16r_rot GPR:$Src, 24)>;
|
||||
def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
|
||||
(UXTB16r_rot GPR:$Src, 8)>;
|
||||
|
||||
defm UXTAB : AI_bin_rrot<"uxtab",
|
||||
defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
|
||||
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
|
||||
defm UXTAH : AI_bin_rrot<"uxtah",
|
||||
defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
|
||||
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
|
||||
}
|
||||
|
||||
@ -1090,15 +1101,15 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
||||
// Misc. Arithmetic Instructions.
|
||||
//
|
||||
|
||||
def CLZ : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
|
||||
def CLZ : AI<(outs GPR:$dst), (ins GPR:$src), ArithMiscFrm,
|
||||
"clz", " $dst, $src",
|
||||
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
|
||||
|
||||
def REV : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
|
||||
def REV : AI<(outs GPR:$dst), (ins GPR:$src), ArithMiscFrm,
|
||||
"rev", " $dst, $src",
|
||||
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
|
||||
|
||||
def REV16 : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
|
||||
def REV16 : AI<(outs GPR:$dst), (ins GPR:$src), ArithMiscFrm,
|
||||
"rev16", " $dst, $src",
|
||||
[(set GPR:$dst,
|
||||
(or (and (srl GPR:$src, 8), 0xFF),
|
||||
@ -1107,7 +1118,7 @@ def REV16 : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
|
||||
(and (shl GPR:$src, 8), 0xFF000000)))))]>,
|
||||
Requires<[IsARM, HasV6]>;
|
||||
|
||||
def REVSH : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
|
||||
def REVSH : AI<(outs GPR:$dst), (ins GPR:$src), ArithMiscFrm,
|
||||
"revsh", " $dst, $src",
|
||||
[(set GPR:$dst,
|
||||
(sext_inreg
|
||||
@ -1116,7 +1127,7 @@ def REVSH : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
|
||||
Requires<[IsARM, HasV6]>;
|
||||
|
||||
def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
|
||||
Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
|
||||
ArithMiscFrm, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
|
||||
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
|
||||
(and (shl GPR:$src2, (i32 imm:$shamt)),
|
||||
0xFFFF0000)))]>,
|
||||
@ -1130,7 +1141,7 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
|
||||
|
||||
|
||||
def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
|
||||
Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
|
||||
ArithMiscFrm, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
|
||||
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
|
||||
(and (sra GPR:$src2, imm16_31:$shamt),
|
||||
0xFFFF)))]>, Requires<[IsARM, HasV6]>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user