mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-01 00:33:09 +00:00
support bsr, and more .td simplification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22543 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
fe660397e1
commit
98169be50b
@ -180,6 +180,9 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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int Offset = 0;
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bool useGOT = false;
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switch (MI.getOpcode()) {
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case Alpha::BSR:
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Reloc = Alpha::reloc_bsr;
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break;
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case Alpha::LDLr:
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case Alpha::LDQr:
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case Alpha::LDBUr:
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@ -859,7 +859,7 @@ void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
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unsigned Opc;
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if (EnableAlphaFTOI) {
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Opc = isDouble ? Alpha::FTOIT : Alpha::FTOIS;
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BuildMI(BB, Opc, 1, dst).addReg(src);
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BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::F31);
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} else {
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//The hard way:
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// Spill the integer to memory and reload it from there.
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@ -886,7 +886,7 @@ void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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unsigned Opc;
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if (EnableAlphaFTOI) {
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Opc = isDouble?Alpha::ITOFT:Alpha::ITOFS;
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BuildMI(BB, Opc, 1, dst).addReg(src);
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BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::R31);
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} else {
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//The hard way:
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// Spill the integer to memory and reload it from there.
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@ -946,7 +946,7 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
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//assert(0 && "Setcc On float?\n");
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std::cerr << "Setcc on float!\n";
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Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1);
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Tmp1 = Tmp3;
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}
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if (SetCC->getOperand(1).getValueType() == MVT::f32)
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@ -954,7 +954,7 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
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//assert (0 && "Setcc On float?\n");
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std::cerr << "Setcc on float!\n";
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Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2);
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Tmp2 = Tmp3;
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}
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@ -1447,10 +1447,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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MoveInt2FP(Tmp1, Tmp4, true);
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MoveInt2FP(Tmp2, Tmp5, true);
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BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Tmp4);
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BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Tmp5);
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BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Alpha::F31).addReg(Tmp4);
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BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Alpha::F31).addReg(Tmp5);
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BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7);
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BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Tmp8);
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BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Alpha::F31).addReg(Tmp8);
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MoveFP2Int(Tmp9, Result, true);
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return Result;
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}
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@ -1925,11 +1925,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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if (SrcType == MVT::f32)
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{
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Tmp2 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
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Tmp1 = Tmp2;
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}
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Tmp2 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
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MoveFP2Int(Tmp2, Result, true);
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return Result;
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@ -2153,7 +2153,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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N.getOperand(0).getValueType() == MVT::f64 &&
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"only f64 to f32 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
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return Result;
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case ISD::FP_EXTEND:
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@ -2161,7 +2161,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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N.getOperand(0).getValueType() == MVT::f32 &&
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"only f32 to f64 conversion supported here");
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
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return Result;
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case ISD::ConstantFP:
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@ -2186,7 +2186,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Tmp2 = MakeReg(MVT::f64);
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MoveInt2FP(Tmp1, Tmp2, true);
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Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
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BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
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BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2);
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return Result;
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}
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}
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@ -153,11 +153,25 @@ class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
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}
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//3.3.4
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class FPForm<bits<6> opcode, bits<11> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
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: InstAlpha<opcode, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), asmstr> {
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bits<5> Fc;
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bits<5> Fa;
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bits<5> Fb;
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bits<11> Function = fun;
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let Inst{25-21} = Fa;
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let Inst{20-16} = Fb;
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let Inst{15-5} = Function;
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let Inst{4-0} = Fc;
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}
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class FPFormCM<bits<6> opcode, bits<11> fun, dag OL, string asmstr>
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: InstAlpha<opcode, OL, asmstr> {
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bits<5> Fc;
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bits<5> Fa;
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bits<5> Fb;
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bits<11> Function = fun;
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let Inst{25-21} = Fa;
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let Inst{20-16} = Fb;
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@ -98,17 +98,17 @@ let isTwoAddress = 1 in {
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"cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
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//conditional moves, fp
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def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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def FCMOVEQ : FPFormCM<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
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def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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def FCMOVGE : FPFormCM<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
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def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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def FCMOVGT : FPFormCM<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
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def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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def FCMOVLE : FPFormCM<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
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def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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def FCMOVLT : FPFormCM<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
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def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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def FCMOVNE : FPFormCM<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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}
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@ -232,10 +232,10 @@ def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quad
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def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
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//Comparison, FP
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def CMPTEQ : FPForm<0x16, 0x0A5, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
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def CMPTLE : FPForm<0x16, 0x0A7, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal
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def CMPTLT : FPForm<0x16, 0x0A6, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than
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def CMPTUN : FPForm<0x16, 0x0A4, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
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def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
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def CMPTLE : FPForm<0x16, 0x0A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal
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def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than
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def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
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//There are in the Multimedia extentions, so let's not use them yet
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def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
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@ -350,37 +350,37 @@ def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
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def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
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//Funky Floating point ops
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def CPYS : FPForm<0x17, 0x020, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpys $RA,$RB,$RC">; //Copy sign
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def CPYSE : FPForm<0x17, 0x022, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpyse $RA,$RB,$RC">; //Copy sign and exponent
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def CPYSN : FPForm<0x17, 0x021, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpysn $RA,$RB,$RC">; //Copy sign negate
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def CPYS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC">; //Copy sign
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def CPYSE : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC">; //Copy sign and exponent
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def CPYSN : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC">; //Copy sign negate
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//Basic Floating point ops
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def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds/su $RA,$RB,$RC">; //Add S_floating
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def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt/su $RA,$RB,$RC">; //Add T_floating
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def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs/su $RA,$RB,$RC">; //Subtract S_floating
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def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt/su $RA,$RB,$RC">; //Subtract T_floating
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def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs/su $RA,$RB,$RC">; //Divide S_floating
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def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt/su $RA,$RB,$RC">; //Divide T_floating
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def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls/su $RA,$RB,$RC">; //Multiply S_floating
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def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult/su $RA,$RB,$RC">; //Multiply T_floating
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def SQRTS : FPForm<0x14, 0x08B, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrts $RA,$RB,$RC">; //Square root S_floating
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def SQRTT : FPForm<0x14, 0x0AB, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrtt $RA,$RB,$RC">; //Square root T_floating
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def ADDS : FPForm<0x16, 0x080, "adds/su $RA,$RB,$RC">; //Add S_floating
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def ADDT : FPForm<0x16, 0x0A0, "addt/su $RA,$RB,$RC">; //Add T_floating
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def SUBS : FPForm<0x16, 0x081, "subs/su $RA,$RB,$RC">; //Subtract S_floating
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def SUBT : FPForm<0x16, 0x0A1, "subt/su $RA,$RB,$RC">; //Subtract T_floating
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def DIVS : FPForm<0x16, 0x083, "divs/su $RA,$RB,$RC">; //Divide S_floating
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def DIVT : FPForm<0x16, 0x0A3, "divt/su $RA,$RB,$RC">; //Divide T_floating
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def MULS : FPForm<0x16, 0x082, "muls/su $RA,$RB,$RC">; //Multiply S_floating
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def MULT : FPForm<0x16, 0x0A2, "mult/su $RA,$RB,$RC">; //Multiply T_floating
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def SQRTS : FPForm<0x14, 0x08B, "sqrts $RA,$RB,$RC">; //Square root S_floating
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def SQRTT : FPForm<0x14, 0x0AB, "sqrtt $RA,$RB,$RC">; //Square root T_floating
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//INT reg to FP reg and back again
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//not supported on 21164
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def FTOIS : FPForm<0x1C, 0x078, (ops FPRC:$RC, GPRC:$RA), "ftois $RA,$RC">; //Floating to integer move, S_floating
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def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Floating to integer move, T_floating
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def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating
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def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //Integer to floating move, T_floating
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def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC">; //Floating to integer move, S_floating
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def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC">; //Floating to integer move, T_floating
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def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC">; //Integer to floating move, S_floating
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def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC">; //Integer to floating move, T_floating
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//CVTLQ F-P 17.010 Convert longword to quadword
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//CVTQL F-P 17.030 Convert quadword to longword
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//These use SW completion, may not have function code for that set right (matters for JIT)
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def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
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def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
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def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtsts $RA,$RC">; //Convert S_floating to T_floating
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def CVTTQ : FPForm<0x16, 0x0AF, (ops FPRC:$RC, FPRC:$RA), "cvttq/svc $RA,$RC">; //Convert T_floating to quadword
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def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts/su $RA,$RC">; //Convert T_floating to S_floating
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def CVTQS : FPForm<0x16, 0x0BC, "cvtqs $RB,$RC">; //Convert quadword to S_floating
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def CVTQT : FPForm<0x16, 0x0BE, "cvtqt $RB,$RC">; //Convert quadword to T_floating
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def CVTST : FPForm<0x16, 0x2AC, "cvtsts $RB,$RC">; //Convert S_floating to T_floating
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def CVTTQ : FPForm<0x16, 0x0AF, "cvttq/svc $RB,$RC">; //Convert T_floating to quadword
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def CVTTS : FPForm<0x16, 0x2AC, "cvtts/su $RB,$RC">; //Convert T_floating to S_floating
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//S_floating : IEEE Single
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//T_floating : IEEE Double
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@ -245,6 +245,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
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for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
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unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
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long idx = 0;
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bool doCommon = true;
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switch ((Alpha::RelocationType)MR->getRelocationType()) {
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default: assert(0 && "Unknown relocation type!");
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case Alpha::reloc_literal:
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@ -289,9 +290,18 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
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assert(0 && "Cannot handle gpdist yet");
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}
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break;
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case Alpha::reloc_bsr: {
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idx = (((unsigned char*)MR->getResultPointer() -
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(unsigned char*)RelocPos) >> 2) + 1; //skip first 2 inst of fun
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*RelocPos |= (idx & ((1 << 21)-1));
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doCommon = false;
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break;
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}
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}
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if (doCommon) {
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short x = (short)idx;
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assert(x == idx);
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*(short*)RelocPos = x;
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}
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short x = (short)idx;
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assert(x == idx);
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*(short*)RelocPos = x;
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}
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}
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@ -23,6 +23,7 @@ namespace llvm {
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reloc_gprellow,
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reloc_gprelhigh,
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reloc_gpdist,
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reloc_bsr,
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};
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}
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}
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