mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 21:32:10 +00:00
[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
47c311bafe
commit
98422af96f
@ -1640,6 +1640,9 @@ multiclass BitfieldImm<bits<2> opc, string asm> {
|
|||||||
def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
|
def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
|
||||||
let Inst{31} = 0;
|
let Inst{31} = 0;
|
||||||
let Inst{22} = 0;
|
let Inst{22} = 0;
|
||||||
|
// imms<5> and immr<5> must be zero, else ReservedValue().
|
||||||
|
let Inst{21} = 0;
|
||||||
|
let Inst{15} = 0;
|
||||||
}
|
}
|
||||||
def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
|
def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
|
||||||
let Inst{31} = 1;
|
let Inst{31} = 1;
|
||||||
@ -1671,6 +1674,9 @@ multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
|
|||||||
def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
|
def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
|
||||||
let Inst{31} = 0;
|
let Inst{31} = 0;
|
||||||
let Inst{22} = 0;
|
let Inst{22} = 0;
|
||||||
|
// imms<5> and immr<5> must be zero, else ReservedValue().
|
||||||
|
let Inst{21} = 0;
|
||||||
|
let Inst{15} = 0;
|
||||||
}
|
}
|
||||||
def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
|
def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
|
||||||
let Inst{31} = 1;
|
let Inst{31} = 1;
|
||||||
|
@ -17,5 +17,7 @@
|
|||||||
# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
|
# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
|
||||||
# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
|
# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
|
||||||
|
|
||||||
|
# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
|
||||||
|
# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
|
||||||
|
|
||||||
# CHECK: invalid instruction encoding
|
# CHECK: invalid instruction encoding
|
||||||
|
Loading…
Reference in New Issue
Block a user