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Remove a register class that can just as well be synthesized.

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Add the new TableGen register class synthesizer feature to the release
notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-12-19 16:53:40 +00:00
parent 0488d6ee5d
commit 9897c622e0
2 changed files with 4 additions and 9 deletions
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5
docs/ReleaseNotes.html
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@ -337,7 +337,10 @@ Release Notes</a>.</h1>
make it run faster:</p>
<ul>
<li>....</li>
<li>TableGen can now synthesize register classes that are only needed to
represent combinations of constraints from instructions and sub-registers.
The synthetic register classes inherit most of their properties form their
closest user-defined super-class.</li>
</ul>
</div>

8
lib/Target/ARM/ARMRegisterInfo.td
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@ -326,14 +326,6 @@ def QQPR : RegisterClass<"ARM", [v4i64], 256, (sequence "QQ%u", 0, 7)> {
let AltOrderSelect = [{ return 1; }];
}
// Subset of QQPR that have 32-bit SPR subregs.
def QQPR_VFP2 : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 4)> {
let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
(DPR_VFP2 dsub_0, dsub_1, dsub_2, dsub_3),
(QPR_VFP2 qsub_0, qsub_1)];
}
// Pseudo 512-bit vector register class to model 4 consecutive Q registers
// (8 consecutive D registers).
def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {