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Privatize an unused part of the LiveIntervalUnion::Query interface.

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No clients are iterating over interference overlaps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137350 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-08-11 21:00:42 +00:00
parent 508e1d3db5
commit 98985f959c
2 changed files with 13 additions and 19 deletions
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29
lib/CodeGen/LiveIntervalUnion.h
View File

@ -187,27 +187,9 @@ public:
return *VirtReg;
}
bool isInterference(const InterferenceResult &IR) const {
if (IR.VirtRegI != VirtReg->end()) {
assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
"invalid segment iterators");
return true;
}
return false;
}
// Does this live virtual register interfere with the union?
bool checkInterference() { return isInterference(firstInterference()); }
// Get the first pair of interfering segments, or a noninterfering result.
// This initializes the firstInterference_ cache.
const InterferenceResult &firstInterference();
// Treat the result as an iterator and advance to the next interfering pair
// of segments. Visiting each unique interfering pairs means that the same
// VirtReg or LiveUnion segment may be visited multiple times.
bool nextInterference(InterferenceResult &IR) const;
// Count the virtual registers in this union that interfere with this
// query's live virtual register, up to maxInterferingRegs.
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
@ -235,7 +217,18 @@ public:
void operator=(const Query&); // DO NOT IMPLEMENT
// Private interface for queries
const InterferenceResult &firstInterference();
bool nextInterference(InterferenceResult &IR) const;
void findIntersection(InterferenceResult &IR) const;
bool isInterference(const InterferenceResult &IR) const {
if (IR.VirtRegI != VirtReg->end()) {
assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
"invalid segment iterators");
return true;
}
return false;
}
};
};

3
lib/CodeGen/RegAllocBasic.cpp
View File

@ -498,8 +498,9 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
// Found an available register.
return PhysReg;
}
Queries[interfReg].collectInterferingVRegs(1);
LiveInterval *interferingVirtReg =
Queries[interfReg].firstInterference().liveUnionPos().value();
Queries[interfReg].interferingVRegs().front();
// The current VirtReg must either be spillable, or one of its interferences
// must have less spill weight.