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https://github.com/c64scene-ar/llvm-6502.git
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Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
03300ecaee
commit
98fc72940b
@ -9515,6 +9515,23 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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case Intrinsic::x86_avx_hsub_pd_256:
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return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_avx2_psllv_d:
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case Intrinsic::x86_avx2_psllv_q:
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case Intrinsic::x86_avx2_psllv_d_256:
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case Intrinsic::x86_avx2_psllv_q_256:
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return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_avx2_psrlv_d:
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case Intrinsic::x86_avx2_psrlv_q:
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case Intrinsic::x86_avx2_psrlv_d_256:
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case Intrinsic::x86_avx2_psrlv_q_256:
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return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_avx2_psrav_d:
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case Intrinsic::x86_avx2_psrav_d_256:
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return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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// ptest and testp intrinsics. The intrinsic these come from are designed to
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// return an integer value, not just an instruction so lower it to the ptest
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// or testp pattern and a setcc for the result.
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@ -7741,111 +7741,62 @@ defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
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//===----------------------------------------------------------------------===//
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// Variable Bit Shifts
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//
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multiclass avx2_var_shift<bits<8> opc, string OpcodeStr,
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Intrinsic Int128, Intrinsic Int256> {
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multiclass avx2_var_shift_i32<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V;
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[(set VR128:$dst,
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(v4i32 (OpNode VR128:$src1, (v4i32 VR128:$src2))))]>,
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VEX_4V;
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def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
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VEX_4V;
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(v4i32 (OpNode VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))))]>, VEX_4V;
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def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V;
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[(set VR256:$dst,
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(v8i32 (OpNode VR256:$src1, (v8i32 VR256:$src2))))]>,
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VEX_4V;
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def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(Int256 VR256:$src1, (bitconvert (memopv4i64 addr:$src2))))]>,
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VEX_4V;
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(v8i32 (OpNode VR256:$src1,
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(bc_v8i32 (memopv4i64 addr:$src2)))))]>, VEX_4V;
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}
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multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr,
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Intrinsic Int128, Intrinsic Int256> {
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multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V;
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[(set VR128:$dst,
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(v2i64 (OpNode VR128:$src1, (v2i64 VR128:$src2))))]>,
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VEX_4V;
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def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
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(v2i64 (OpNode VR128:$src1, (memopv2i64 addr:$src2))))]>,
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VEX_4V;
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def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V;
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[(set VR256:$dst,
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(v4i64 (OpNode VR256:$src1, (v4i64 VR256:$src2))))]>,
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VEX_4V;
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def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(Int256 VR256:$src1, (memopv4i64 addr:$src2)))]>,
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(v4i64 (OpNode VR256:$src1, (memopv4i64 addr:$src2))))]>,
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VEX_4V;
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}
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defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", int_x86_avx2_psllv_d,
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int_x86_avx2_psllv_d_256>;
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defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", int_x86_avx2_psllv_q,
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int_x86_avx2_psllv_q_256>, VEX_W;
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defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", int_x86_avx2_psrlv_d,
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int_x86_avx2_psrlv_d_256>;
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defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", int_x86_avx2_psrlv_q,
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int_x86_avx2_psrlv_q_256>, VEX_W;
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defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", int_x86_avx2_psrav_d,
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int_x86_avx2_psrav_d_256>;
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let Predicates = [HasAVX2] in {
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def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
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(VPSLLVDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
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(VPSLLVQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
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(VPSRLVDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
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(VPSRLVQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
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(VPSRAVDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
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(VPSLLVDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
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(VPSLLVQYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
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(VPSRLVDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
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(VPSRLVQYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
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(VPSRAVDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i32 (shl (v4i32 VR128:$src1),
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(bc_v4i32 (memopv2i64 addr:$src2)))),
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(VPSLLVDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
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(VPSLLVQrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (srl (v4i32 VR128:$src1),
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(bc_v4i32 (memopv2i64 addr:$src2)))),
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(VPSRLVDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
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(VPSRLVQrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (sra (v4i32 VR128:$src1),
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(bc_v4i32 (memopv2i64 addr:$src2)))),
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(VPSRAVDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i32 (shl (v8i32 VR256:$src1),
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(bc_v8i32 (memopv4i64 addr:$src2)))),
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(VPSLLVDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
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(VPSLLVQYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (srl (v8i32 VR256:$src1),
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(bc_v8i32 (memopv4i64 addr:$src2)))),
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(VPSRLVDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
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(VPSRLVQYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (sra (v8i32 VR256:$src1),
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(bc_v8i32 (memopv4i64 addr:$src2)))),
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(VPSRAVDYrm VR256:$src1, addr:$src2)>;
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}
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defm VPSLLVD : avx2_var_shift_i32<0x47, "vpsllvd", shl>;
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defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", shl>, VEX_W;
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defm VPSRLVD : avx2_var_shift_i32<0x45, "vpsrlvd", srl>;
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defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", srl>, VEX_W;
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defm VPSRAVD : avx2_var_shift_i32<0x46, "vpsravd", sra>;
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