From 9935bd0819dcc3fe316a7c5c25ee245540df2ecf Mon Sep 17 00:00:00 2001
From: Richard Osborne <richard@xmos.com>
Date: Wed, 23 Feb 2011 18:35:59 +0000
Subject: [PATCH] Add llvm.xcore.waitevent intrinsic. The effect of this
 intrinsic is to enable events on the thread and wait until a resource is
 ready to event. The vector of the resource that is ready is returned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/IntrinsicsXCore.td    |  3 +++
 lib/Target/XCore/XCoreInstrInfo.td |  8 +++++++-
 test/CodeGen/XCore/events.ll       | 21 +++++++++++++++++++++
 3 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/XCore/events.ll

diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td
index 854714eec4f..85fa00d6665 100644
--- a/include/llvm/IntrinsicsXCore.td
+++ b/include/llvm/IntrinsicsXCore.td
@@ -47,4 +47,7 @@ let TargetPrefix = "xcore" in {  // All intrinsics start with "llvm.xcore.".
                                   [NoCapture<0>]>;
   def int_xcore_setv : Intrinsic<[],[llvm_anyptr_ty, llvm_ptr_ty],
                                  [NoCapture<0>]>;
+
+  // Intrinsics for events.
+  def int_xcore_waitevent : Intrinsic<[llvm_ptr_ty],[], [IntrReadMem]>;
 }
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index b89f6769971..90a725220f2 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -895,7 +895,7 @@ def SETV_1r : _F1R<(outs), (ins GRRegs:$r),
                [(int_xcore_setv GRRegs:$r, R11)]>;
 
 // Zero operand short
-// TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
+// TODO clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
 // dentsp, drestsp
 
@@ -904,6 +904,12 @@ def GETID_0R : _F0R<(outs), (ins),
                  "get r11, id",
                  [(set R11, (int_xcore_getid))]>;
 
+let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
+    hasSideEffects = 1 in
+def WAITEU_0R : _F0R<(outs), (ins),
+                 "waiteu",
+                 [(brind (int_xcore_waitevent))]>;
+
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/XCore/events.ll b/test/CodeGen/XCore/events.ll
new file mode 100644
index 00000000000..32b5a60977c
--- /dev/null
+++ b/test/CodeGen/XCore/events.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
+declare i8* @llvm.xcore.waitevent()
+
+define i32 @f(i8 addrspace(1)* %r) nounwind {
+; CHECK: f:
+entry:
+  call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* blockaddress(@f, %L1))
+  call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* blockaddress(@f, %L2))
+  %goto_addr = call i8* @llvm.xcore.waitevent()
+; CHECK: waiteu
+  indirectbr i8* %goto_addr, [label %L1, label %L2]
+L1:
+  br label %ret
+L2:
+  br label %ret
+ret:
+  %retval = phi i32 [1, %L1], [2, %L2]
+  ret i32 %retval
+}