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Have SPU handle halfvec stores aligned by 8 bytes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila
2010-08-09 16:33:00 +00:00
parent c1f354dcb8
commit 99534bb81a
7 changed files with 72 additions and 12 deletions
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6
test/CodeGen/CellSPU/bigstack.ll
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@@ -1,7 +1,7 @@
; RUN: llc < %s -march=cellspu -o %t1.s
; RUN: grep lqx %t1.s | count 4
; RUN: grep il %t1.s | grep -v file | count 7
; RUN: grep stqx %t1.s | count 2
; RUN: grep lqx %t1.s | count 3
; RUN: grep il %t1.s | grep -v file | count 5
; RUN: grep stqx %t1.s | count 1
define i32 @bigstack() nounwind {
entry:

12
test/CodeGen/CellSPU/v2f32.ll
View File

@@ -61,3 +61,15 @@ define %vec @test_insert(){
ret %vec %rv
}
define void @test_unaligned_store() {
;CHECK: cdd $3, 8($3)
;CHECK: lqd
;CHECK: shufb
;CHECK: stqd
%data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1]
%ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1]
%vptr = bitcast float* %ptr to <2 x float>* ; <[1 x <2 x float>]*> [#uses=1]
store <2 x float> undef, <2 x float>* %vptr
ret void
}