Revert r235869 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

It introduced two regressions (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) on 3 out of 23 cross-compilation
test-runs used by Mips for release validation.

The issue is that on 64-bit targets comparisons such as BEQ compare the whole
GPR64 but incorrectly tell the instruction selector that they operate on
GPR32's. This leads to the elimination of i32->i64 extensions that are actually
required by comparisons to work correctly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237432 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/Mips/llvm-ir/and.ll

@@ -51,7 +51,10 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         sll     $2, $[[T0]], 0
 
   %r = and i32 %a, %b
   ret i32 %r

test/CodeGen/Mips/llvm-ir/or.ll

@@ -51,7 +51,11 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or     $2, $4, $5
+
+  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
+  ; FIXME: The sll instruction below is redundant.
+  ; GP64:         sll     $2, $[[T0]], 0
 
   %r = or i32 %a, %b
   ret i32 %r

test/CodeGen/Mips/llvm-ir/xor.ll

@@ -51,7 +51,10 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         sll     $2, $[[T0]], 0
 
   %r = xor i32 %a, %b
   ret i32 %r